MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1547

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the core complex, is always among the bits saved and restored; hence these outputs negate to the
MPC8536E power management logic when the interrupt begins processing in the core. They return to their
previous state when the core executes an rfi, rfci, or rfmci instruction.
23.5.1.9.2
The IRQ_MSK and CI_MSK fields of the POWMGTCSR register prevent int interrupts or cint critical
interrupts from waking the device from a low power state. This is true regardless of the method used to
enter the low power state.
Any unmasked interrupt (not masked by the mask bits in the POWMGTCSR register) causes the
POWMGTCSR[DOZ,SLP,DPSLP] fields to be cleared when it occurs. When such an interrupt occurs, the
device returns to the normal operating mode and does not automatically attempt to return to a low power
state after the interrupt is handled.
Note that interrupts caused by the unconditional debug event (UDE) and machine check (MCP) signals are
not masked by the IRQ_MSK and CI_MSK fields; therefore, when these signals assert, the
POWMGTCSR[DOZ,SLP,DPSLP] fields are cleared and the device will return to full power operation.
See
information about the bits of POWMGTCSR.
Note also that unmasked interrupts that occur while the device is in the process of going into the sleep state
(before sleep is completely attained) can also cause the device to clear the
POWMGTCSR[DOZ,SLP,DPSLP] fields and return the device to full power operation. In particular for
deep sleep, this means that the setting of POWMGTCSR[DPSLP] does not guarantee that the core will be
reset if an interrupt arrives in this situation.
23.5.1.10 Snooping in Power-Down Modes (e500)
When the MPC8536E is in doze mode, the e500 core is in the core-halted state and it snoops its L1 caches
and full coherency is maintained. In deeper power-down modes, however, the e500 core does not respond
to snoops. The MPC8536E does not perform dynamic bus snooping as described in the e500 Reference
Manual. That is, when the e500 core is in the core-stopped state (which is the state of the core when the
MPC8536E is in either the nap or sleep state), the core is not awakened to perform snoops on global
transactions. Therefore, before entering nap, sleep or deep sleep modes, the L1 caches should be flushed
if coherency is required during these power-down modes.
23.5.1.11 Software Considerations for Power Management (e500)
Setting MSR[WE] generates a request to the MPC8536E logic (external to the core complex) to enter a
power saving state. It is assumed that the desired power-saving state (doze, nap, or sleep) was set up by
Freescale Semiconductor
Section 23.4.1.12, “Power Management Control and Status Register (POWMGTCSR),”
Returning doze, nap, and sleep signals to their original state when
MSR[WE] is restored differs from low power management is implemented
on earlier PowerPC devices where MSR[POW], which enables power-down
requests, is cleared when the processor exits a low-power state and is not
automatically restored, as it is in Book E implementations.
Interrupts and Power Management Controlled by POWMGTCSR (e500)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
NOTE
for detailed
Global Utilities
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