MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1078
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MPC8536E-ANDROID
Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr
Datasheets
1.MPC8536EBVTAVLA.pdf
(127 pages)
2.MPC8536EBVTAVLA.pdf
(2 pages)
3.MPC8536EBVTAVLA.pdf
(1706 pages)
Specifications of MPC8536E-ANDROID
Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PCI Bus Interface
Figure 16-51
Figure 16-52
16.4.2.8
A PCI transaction may be terminated by either the initiator or the target. The initiator is ultimately
responsible for concluding all transactions, regardless of the cause of the termination. All transactions are
concluded when PCI_FRAME and PCI_IRDY are both negated, indicating the bus is idle.
16.4.2.8.1
Normally, a master initiates termination by negating PCI_FRAME and asserting PCI_IRDY. This
indicates to the target that the final data phase is in progress. The final data transfer occurs when both
PCI_TRDY and PCI_IRDY are asserted. The transaction is considered complete when data is transferred
16-52
PCI_DEVSEL
PCI_FRAME
PCI_FRAME
PCI_EVSEL
PCI_TRDY
PCI_TRDY
PCI_C/BE
PCI_IRDY
PCI_C/BE
PCI_IRDY
Transaction Termination
illustrates a PCI single-beat write transaction.
illustrates a PCI burst write transaction.
SYSCLK
SYSCLK
PCI_AD
PCI_AD
Master-Initiated Termination
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 16-51. PCI Single-Beat Write Transaction
ADDR
ADDR
CMD
CMD
Figure 16-52. PCI Burst Write Transaction
Byte Enables 1 Byte Enables 2
DATA1
DATA2
Byte Enables
DATA
Byte Enables 3
DATA3
DATA4
BEs 4
Freescale Semiconductor
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