MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1241

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.3.2.7.1
On single device error:
On fatal error:
Freescale Semiconductor
1. Examine the register DER to determine which device is in error state. There might be multiple
2. Examine the register CER to determine which command was in error. The software knows which
3. Examine the status location of the descriptor of the command in error and determine the reason for
4. If needed, the software should send commands to the device to clear down the error condition on
5. Clear the DERn bit by writing 1 to bit n, where n indicates the device in error. This will also clear
6. Clear the CERn bit by writing 1 to bit n, where n indicates the associated command in error. After
1. Read the error register and other registers to determine how many commands are outstanding and
2. Bring the SATA controller offline. When this happens all queues within the SATA controller will
3. Perform what corrective action the software determines is necessary.
4. Bring the SATA controller online. This will cause an out-of-bounds (OOB) to be run at the PHY
Bit
1
0
devices in error.
command belongs to which device.
the error.
device or for further examination of the device's status.
out the outstanding commands for that device.
that, the software can reissue command to the device if needed.
how many have completed without error.
be cleared.
level which will clear down any attached device.
Name
DE
CC
Error Processing
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Device error. When set, this bit indicates that the DE register has at least one bit set. In this state,
the interrupt will be generated if DE_INT is set in the host control register. Write ‘1’ to clear the
interrupt source.
Command complete. When set, this bit indicates that the register CCR has at least one bit set. In
this state, the interrupt will be generated if CC_INT is set in the host control register. Write ‘1’ to
clear the interrupt source.
Table 19-8. HStatus Field Descriptions (continued)
Description
SATA Controller
19-11