MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 286

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
1
8.4.1
This section describes the DDR memory controller registers. Shading indicates reserved fields that should
not be written.
8.4.1.1
The chip select bounds registers (CSn_BNDS) define the starting and ending address of the memory space
that corresponds to the individual chip selects. Note that the size specified in CSn_BNDS should equal the
size of physical DRAM. Also, note that EAn must be greater than or equal to SAn.
If chip select interleaving is enabled, all fields in the lower interleaved chip select are used, and the other
chip selects’ bounds registers are unused. For example, if chip selects 0 and 1 are interleaved, all fields in
CS0_BNDS are used, and all fields in CS1_BNDS are unused.
8-12
0xB30–
0x188–
0xB2C
0xBFC
0xE4C
Offset
0xB1F
0xBF7
0xBF8
0xB20
0xB24
0xB28
0xE00
0xE04
0xE08
0xE20
0xE24
0xE28
0xE40
0xE44
0xE48
0xE50
0xE54
0xE58
Implementation-dependent reset values are listed in specified section/page.
Reserved
DDRDSR_1—DDR Debug Status Register 1
DDRDSR_2—DDR Debug Status Register 2
DDRCDR_1—DDR Control Driver Register 1
DDRCDR_2—DDR Control Driver Register 2
Reserved
DDR_IP_REV1—DDR IP block revision 1
DDR_IP_REV2—DDR IP block revision 2
DATA_ERR_INJECT_HI—Memory data path error injection mask high
DATA_ERR_INJECT_LO—Memory data path error injection mask low
ERR_INJECT—Memory data path error injection mask ECC
CAPTURE_DATA_HI—Memory data path read capture high
CAPTURE_DATA_LO—Memory data path read capture low
CAPTURE_ECC—Memory data path read capture ECC
ERR_DETECT—Memory error detect
ERR_DISABLE—Memory error disable
ERR_INT_EN—Memory error interrupt enable
CAPTURE_ATTRIBUTES—Memory error attributes capture
CAPTURE_ADDRESS—Memory error address capture
CAPTURE_EXT_ADDRESS—Memory error extended address capture
ERR_SBE—Single-Bit ECC memory error management
Register Descriptions
Chip Select Memory Bounds (CS n _BNDS)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 8-5. DDR Memory Controller Memory Map (continued)
Register
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
—
—
R
R
R
R
0x nnnn _ nnnn
0x00 nn _00 nn
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
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Freescale Semiconductor
1
1
Section/Page
8.4.1.25/8-46
8.4.1.26/8-47
8.4.1.27/8-47
8.4.1.28/8-50
8.4.1.29/8-50
8.4.1.30/8-51
8.4.1.31/8-51
8.4.1.32/8-52
8.4.1.33/8-52
8.4.1.34/8-53
8.4.1.35/8-54
8.4.1.36/8-54
8.4.1.37/8-54
8.4.1.38/8-56
8.4.1.39/8-57
8.4.1.40/8-58
8.4.1.41/8-58
8.4.1.42/8-59
8.4.1.43/8-59
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