MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1159

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MPC8536E-ANDROID

Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr

Specifications of MPC8536E-ANDROID

Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
17.3.8.3.11 PCI Express Prefetchable Memory Base Register—0x24
The prefetchable memory base register is shown in
Table 17-66
17.3.8.3.12 PCI Express Prefetchable Memory Limit Register—0x26
The prefetchable memory limit register is shown in
Table 17-67
Freescale Semiconductor
Offset 0x24
Reset
Offset 0x26
Reset
W
W
R
R
15–4
15–4
15
15
Bits
Bits
3–0
3–0
describes the prefetchable memory base register fields.
describes the prefetchable memory limit register fields.
Table 17-66. PCI Express Prefetchable Memory Base Register Field Description
Table 17-67. PCI Express Prefetchable Memory Limit Register Field Description
Address Decode Type Specifies the number of prefetchable memory address bits.
Address Decode Type Specifies the number of prefetchable memory address bits.
PF Memory Base
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
PF Memory Limit
Figure 17-68. PCI Express Prefetchable Memory Base Register
Figure 17-69. PCI Express Prefetchable Memory Limit Register
Name
Name
PF Memory Base
PF Memory Limit
Specifies bits 31:20 of the prefetchable memory space start address.
0x00 32-bit memory address decode
0x01 64-bit memory address decode
All other settings reserved.
Specifies bits 31:20 of the prefetchable memory space ending address.
0x00 32-bit memory address decode
0x01 64-bit memory address decode
All other settings reserved.
Figure
Figure
All zeros
All zeros
17-68.
17-69.
Description
Description
4
4
PCI Express Interface Controller
3
3
Address Decode Type
Address Decode Type
Access: Read/Write
Access: Read/Write
17-63
0
0

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