MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 97

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table
Number
17-4
17-5
17-6
17-7
17-8
17-9
17-10
17-11
17-12
17-13
17-14
17-15
17-16
17-17
17-18
17-19
17-20
17-21
17-22
17-23
17-24
17-25
17-26
17-27
17-28
17-29
17-30
17-31
17-32
17-33
17-34
17-35
Freescale Semiconductor
PEX_CONFIG_ADDR Field Descriptions ........................................................................ 17-10
PEX_CONFIG_DATA Field Descriptions ......................................................................... 17-11
PEX_OTB_CPL_TOR Field Descriptions ......................................................................... 17-11
PEX_CONF_RTY_TOR Field Descriptions ...................................................................... 17-12
PEX_CONFIG Field Descriptions...................................................................................... 17-13
PEX_PME_MES_DR Field Descriptions........................................................................... 17-13
PEX_PME_MES_DISR Field Descriptions ....................................................................... 17-15
PEX_PME_MES_IER Field Descriptions.......................................................................... 17-17
PEX_PMCR Field Descriptions.......................................................................................... 17-18
PCI Express IP Block Revision Register 1 Field Descriptions........................................... 17-19
PCI Express IP Block Revision Register 2 Field Descriptions........................................... 17-19
PEXOTARn Field Descriptions .......................................................................................... 17-21
PCI Express Outbound Extended Address Translation Register n Field Descriptions....... 17-21
PCI Express Outbound Window Base Address Register n Field Descriptions................... 17-22
PEXOWARn Field Descriptions ......................................................................................... 17-23
PCI Express Inbound Translation Address Registers Field Descriptions ........................... 17-26
PCI Express Inbound Window Base Address Register Field Descriptions ........................ 17-27
PCI Express Inbound Window Base Extended Address Register Field Descriptions ........ 17-28
PCI Express Inbound Window Attributes Registers Field Descriptions............................. 17-28
PCI Express Error Detect Register Field Descriptions ....................................................... 17-31
PCI Express Error Interrupt Enable Register Field Descriptions ....................................... 17-33
PCI Express Error Disable Register Field Descriptions ..................................................... 17-34
PCI Express Error Capture Status Register Field Descriptions .......................................... 17-36
PCI Express Error Capture Register 0 Field Descriptions
PCI Express Error Capture Register 0 Field Descriptions
PCI Express Error Capture Register 1 Field Descriptions
PCI Express Error Capture Register 1 Field Descriptions
PCI Express Error Capture Register 1 Field Descriptions
PCI Express Error Capture Register 2 Field Descriptions
PCI Express Error Capture Register 2 Field Descriptions
PCI Express Error Capture Register 2 Field Descriptions
PCI Express Error Capture Register 3 Field Descriptions
Internal Source, Outbound Transaction.......................................................................... 17-37
External Source, Inbound Transaction ........................................................................... 17-38
Internal Source, Outbound Transaction.......................................................................... 17-39
External Source, Inbound CompletionTransaction ........................................................ 17-39
External Source, Inbound Memory Request Transaction .............................................. 17-40
Internal Source, Outbound Transaction.......................................................................... 17-40
External Source, Inbound Completion Transaction ....................................................... 17-41
External Source, Inbound Memory Request Transaction .............................................. 17-41
Internal Source, Outbound Transaction.......................................................................... 17-42
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Tables
Title
Number
Page
xcvii