MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 360

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
8.5.12
The DDR memory controller detects four different kinds of errors: training, single-bit, multi-bit, and
memory select errors. The following discussion assumes all the relevant error detection, correction, and
reporting functions are enabled as described in
(ERR_INT_EN),” Section 8.4.1.38, “Memory Error Disable (ERR_DISABLE),”
“Memory Error Detect (ERR_DETECT).”
Single-bit errors are counted and reported based on the ERR_SBE value. When a single-bit error is
detected, the DDR memory controller does the following:
If a multi-bit error is detected for a read, the DDR memory controller logs the error and generates the
machine check or critical interrupt (if enabled, as described in
(ERR_DISABLE)”). Another error the DDR memory controller detects is a memory select error, which
causes the DDR memory controller to log the error and generate a critical interrupt (if enabled, as
described in
address from the memory request does not fall into any of the enabled, programmed chip select address
ranges. For all memory select errors, the DDR memory controller does not issue any transactions onto the
pins after the first read has returned data strobes. If the DDR memory controller is not using sample points,
then a dummy transaction is issued to DDR SDRAM with the first enabled chip select. In this case, the
source port on the pins is forced to 0x1F to show the transaction is not real.
with their descriptions. The final error the memory controller detects is the automatic calibration error.
This error is set if the memory controller detects an error during its training sequence.
8-86
•
•
•
•
Corrects the data
Increments the single-bit error counter ERR_SBE[SBEC]
Generates a critical interrupt if the counter value ERR_SBE[SBEC] equals the programmable
threshold ERR_SBE[SBET]
Completes the transaction normally
Error Management
Section 8.4.1.37, “Memory Error Detect
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 8-66. DDR SDRAM ECC Syndrome Encoding (Check Bits)
Check
Bit
0
1
2
3
4
5
6
7
0
•
1
•
Section 8.4.1.39, “Memory Error Interrupt Enable
2
•
Syndrome Bit
(ERR_DETECT)”). This error is detected if the
3
•
4
•
Section 8.4.1.38, “Memory Error Disable
5
•
6
•
7
•
Table 8-67
and
Freescale Semiconductor
Section 8.4.1.37,
shows the errors