MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 459

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

As shown in
chain of link tables specifies only that parcel (this is the most common situation). In other cases, the
descriptor POINTER is used multiple times to access a sequence of parcels, and the chain of link tables
must supply data for the entire sequence.
10.3.4.1
To further clarify the link table’s operation, we explain in detail the case where the fourth pointer dword
in the descriptor in
Pointer3 is used to access successive parcels of size Extent3, Length3, and Extent4 respectively (refer to
Table 10-10
Since the J3 bit is set, Pointer3 is used as the address of a link table and not a data address. The channel
begins by reading the first four dwords of the link table starting at Pointer3 into an internal “gather table
buffer”.
Using the first entry of the gather table buffer, the channel starts accessing the parcel by reading SEGLEN
bytes beginning at SEGPTR. If the required parcel size (specified by ‘Extent3’ in the pointer dword) is
greater than this first segment length, the channel moves on to the next entry of the gather table buffer, and
reads SEGLEN bytes starting at SEGPTR. This process continues as long as there are more bytes to be
read in the parcel. If all the link table entries in the channel’s gather table buffer have been exhausted, then
the channel reads the next four dwords of the link table into its gather table buffer. If a gather table buffer
entry is encountered in which the N bit is set, the channel uses the SEGPTR field in that word to find the
next link table in the chain.
Now assume that the channel accesses its next parcel using Pointer3 again, this time with length given by
Length3. In this case the channel continues to the next line of the link table, and begins reading the memory
segment specified there. As before, the channel concatenates memory segments from as many link table
entries as necessary to obtain the required number of bytes (Length3).
Similarly, the next parcel is obtained by using Pointer3 yet again, this time with length given by Extent4.
Assume that for the current descriptor type, the Extent4 parcel is the last one to be accessed through
Pointer3. Then the link table entry that supplies the last memory segment for Extent4 has the R bit set,
signifying that this is the last entry in the chain of link tables.
Freescale Semiconductor
for the significance of POINTER, EXTENT, and LENGTH fields in various descriptor types).
Figure
Example of Link Table Operation
The link table or chain of link tables accessed through a descriptor pointer
must specify enough memory segments to hold precisely all the data that
will be accessed through that pointer. This means that the combined lengths
of the parcels associated with that pointer (where each parcel length is
specified by a particular LENGTH or EXTENT field in the descriptor) must
equal the combined lengths of the link table memory segments (SEGLEN
fields). Otherwise the channel sets the error state in the SGLM bit of the
channel status register (see
(CSR)”).
Figure 10-6
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
10-6, in some cases a single parcel is accessed through a given POINTER, and the
is used to access parcels. We suppose that the descriptor type is such that
Section 10.4.4.2, “Channel Status Register
NOTE
Security Engine (SEC) 3.0
10-29