MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 896

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.6.1.3
This section describes the gigabit media-independent interface (GMII) intended to be used between the
PHYs and the eTSEC.
required to establish the eTSEC module connection with a PHY.
A GMII interface has 28 signals (TSECn_GTX_CLK + EC_GTX_CLK125 included), as defined by the
IEEE 802.3u standard, for connecting to an Ethernet PHY.
14.6.1.4
This section describes the reduced gigabit media-independent interface (RGMII) intended to be used
between the PHYs and the GMII MAC. The RGMII is an alternative to the IEEE802.3u MII, the
IEEE802.3z GMII and the TBI. The RGMII reduces the number of signals required to interconnect the
MAC and the PHY from a maximum of 28 signals (GMII) to 15 signals (GTX_CLK125 included) in a cost
effective and technology independent manner. To accomplish this objective, the data paths and all
associated control signals are multiplexed using both edges of the clock. For gigabit operation, the clocks
operate at 125MHz, and for 10/100 operation, the clocks operate at 2.5 MHz or 25 MHz, respectively. Note
that the GTX_CLK125 input must be provided at 125 MHz for an RGMII interface, regardless of operation
speed (1 Gbps, 100 Mbps, or 10 Mbps).
media-independent interface and the signals required to establish the gigabit Ethernet controllers’ module
14-148
1
The management signals (MDC and MDIO) are common to all of the Ethernet controllers’ connections
in the system, assuming that each PHY has a different management address.
eTSEC
Gigabit Media-Independent Interface (GMII)
Reduced Gigabit Media-Independent Interface (RGMII)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 14-134
Gigabit Transmit Clock (TSEC n _GTX_CLK)
Gigabit Reference Clock (GTX_CLK125)
Transmit Nibble Data (TSEC n _TXD[7:0])
Receive Nibble Data (TSEC n _RXD[7:0])
Receive Data Valid (TSEC n _RX_DV)
Carrier Sense Output (TSEC n _CRS)
Figure 14-134. eTSEC-GMII Connection
Transmit Enable (TSEC n _TX_EN)
Transmit Clock (TSEC n _TX_CLK)
Receive Clock (TSEC n _RX_CLK)
Management Data Clock
Transmit Error (TSEC n _TX_ER)
Receive Error (TSEC n _RX_ER)
Management Data I/O
depicts the basic components of the GMII including the signals
Figure 14-135
1
depicts the basic components of the gigabit reduced
1
(MDIO)
(MDC)
Ethernet
Gigabit
PHY
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