MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 284

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
8.3.2.2
Table 8-4
8.3.2.3
The debug signals MSRCID[0:4] and MDVAL have no function in normal DDR controller operation. A
detailed description of these signals can be found in
8.4
Table 8-5
In this table and in the register figures and field descriptions, the following access definitions apply:
8-10
Offset
0x000
0x008
MCKE[0:3]
MCK[0:5],
MCK[0:5]
•
•
•
•
•
Signal
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
CS0_BNDS—Chip select 0 memory bounds
CS1_BNDS—Chip select 1 memory bounds
Memory Map/Register Definition
contains the detailed descriptions of the clock signals of the DDR controller.
shows the register memory map for the DDR memory controller.
Clock Interface Signals
Debug Signals
I/O
O
O
DRAM clock outputs and their complements. See
Clock enable. Output signals used as the clock enables to the SDRAM. MCKE[0:3] can be negated to stop
clocking the DDR SDRAM. The MCKE signals should be connected to the same rank of memory as the
corresponding MCS and MODT signals. For example, MCKE[0] should be connected to the same rank of
memory as MCS[0] and MODT[0].
Meaning
Meaning
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Timing Assertion/Negation—Timing is controlled by the DDR_CLK_CNTL register at offset 0x130.
Timing Assertion/Negation—Asserted when DDR_SDRAM_CFG[MEM_EN] is set. Can be negated
State
State
Table 8-4. Clock Signals—Detailed Signal Descriptions
Asserted/Negated—The JEDEC DDR SDRAM specifications require true and complement
Asserted—Clocking to the SDRAM is enabled.
Negated—Clocking to the SDRAM is disabled and the SDRAM should ignore signal transitions
High impedance—Always driven.
DDR Memory Controller—Block Base Address 0x0_2000
Table 8-5. DDR Memory Controller Memory Map
clocks. A clock edge is seen by the SDRAM when the true and complement cross.
on MCK or MCK. MCK/MCK are don’t cares while MCKE[0:3] are negated.
when entering dynamic power management or self refresh. Are asserted again when
exiting dynamic power management or self refresh.
Register
Section 25.4.2, “DDR SDRAM Interface
Description
Section 8.5.4.1, “Clock Distribution.”
Access
R/W
R/W
0x0000_0000
0x0000_0000
Reset
Freescale Semiconductor
Section/Page
8.4.1.1/8-12
8.4.1.1/8-12
Debug.”