MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 147

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General utilities registers are accessed as 32-bit quantities except for the DUART and I
are accessed as bytes.
2.3.5
The programmable interrupt controller (PIC) registers are at offset 0x4_0000 from CCSRBAR, see
Figure
should only be accessed with 32-bit accesses.
2.3.6
The device-specific registers consist of power management, performance monitors, and device-wide
debug utilities (refer to
of other than 32-bit are considered a programming error and operation is undefined.
Reserved bits in the following register descriptions are not guaranteed to have predictable values. Software
must preserve the values of reserved bits when writing to a register. Also, when reading from a register,
software should not rely on the value of any reserved bit remaining consistent.
Freescale Semiconductor
2-7. Its programming model follows the OpenPIC architecture. The interrupt controller registers
Interrupt Controller and CCSR
Device-Specific Utilities
0xF FFFF
0x0 0000
0x4 0000
0x8 0000
0xE 0000
CCSR Register Memory Block
Figure 2-7. PIC Mapping to Configuration, Control, and Status Memory Block
Refer to detailed register descriptions for each functional unit for exact
locations, sizes, and access requirements. Some blocks may have exceptions
to the above guidelines.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure
Device-Specific
Reserved
General
Utilities
Utilities
PIC
2-8). These registers are accessible with 32-bit accesses only. Transactions
NOTE
0x7 FFFF
0x4 0000
0x4 1000
0x4 1200
0x5 1020
0x4 1100
0x5 0000
0x6 0000
PIC Registers
External IRQs
Internal IRQs
Global Cfg
Processor
Timers
2
C registers, which
Memory Map
2-13