MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1234

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller
19.3.1
Table 19-1
defined for both SATA hosts. That is, SATA1 starts at 0x1_8000 address offset and SATA2 at 0x1_9000.
Undefined 4-byte address spaces within offset 0x000–0xFFF are reserved.
In this table, and in the register figures and field descriptions, the following access definitions apply:
19-4
Offset
0x02C
0x000
0x008
0x010
0x018
0x020
0x024
0x028
0x030
0x034
0x038
0x100
0x104
shows the memory map for the SATA registers. The offsets to the memory map table are
SATA Memory Map/Register Definition
CQR—Command queue register
CAR—Command active register
CCR—Command completed register
CER—Command error register
DE—Device error register
CHBA—Command header base address
HStatus—Host status register
HControl—Host control register
CQPMP—Port number queue register
SIG—Signature register
ICC—Interrupt coalescing control register
SStatus—SATA interface status register
SError—SATA interface error register
All registers (except SYSPR) described in this section and descriptors
described in
“Command Descriptor,”
on the local processor in big-endian mode must byte-swap the data.
•
•
•
•
Reserved fields are always ignored for the purposes of determining
access type.
‘R/W’, ‘R’, and ‘W’ (read/write, read only, and write only) indicate that
all the non-reserved fields in a register have the same access type.
‘w1c’ indicates that all of the non-reserved fields in a register are cleared
by writing ones to them.
‘Mixed’ indicates a combination of access types.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 19.3.6, “Command Header,”
Table 19-1. SATA Register Summary
SATA1—Block Base Address: 0x1_8000
Register
use little-endian byte ordering. Software running
SATA Command Registers
SATA1 Superset Registers
NOTE
and
Access
Mixed
R/W
R/W
R/W
R/W
w1c
w1c
w1c
w1c
w1c
R
R
R
Section 19.3.7,
0xFFFF_FFFF
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x2000_0000
0x0000_0100
0x0000_0000
0x0100_0000
0x0000_0000
0x0000_0000
Reset Value
Freescale Semiconductor
19.3.2.10/19-14
19.3.2.11/19-14
19.3.2.8/19-12
19.3.2.9/19-13
19.3.3.1/19-15
19.3.3.2/19-16
Section/Page
19.3.2.1/19-5
19.3.2.2/19-6
19.3.2.3/19-6
19.3.2.4/19-7
19.3.2.5/19-8
19.3.2.6/19-8
19.3.2.7/19-9