MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1142

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
Table 17-38
17.3.8.1.3
The command register, shown in
to PCI Express cycles.
Table 17-39
17-46
Offset 0x04
Reset
15–11
Bits
10
9
8
7
Offset 0x02
Reset
W
R
W
R
15
Interrupt
Disable
15–0
Name
SERR
15
Bits
—
—
—
describes the device ID register fields.
describes the bits of the command register.
—
PCI Express Command Register—Offset 0x04
Reserved
Controls the ability to generate INTx interrupt messages.
0 Enables INTx interrupt messages
1 Disables INTx interrupt messages
Any INTx emulation interrupts already asserted by this device must be deasserted when this bit is set.
Reserved
Controls the reporting of fatal and non-fatal errors detected by the device to the root complex.
0 Disables reporting
1 Enables reporting
Note: The error control and status bits in the command and status registers control PCI-compatible error
Reserved
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 17-39. PCI Express Command Register Field Descriptions
11
Table 17-38. PCI Express Device ID Register Field Description
Device ID
Name
reporting. PCI Express advanced error reporting is controlled by the PCI Express device control
register described in
advance error reporting capability structure described in sections 17.3.10.1 through 17.3.10.12.
Interrupt
Disable
10
Figure 17-39. PCI Express Command Register
Figure 17-38. PCI Express Device ID Register
Figure
—
9
0x0050 MPC8536E
0x0051 MPC8536
17-39, provides control over the ability to generate and respond
Device-specific; see field description
SERR
Section 17.3.9.8, “PCI Express Device Control
8
—
7
Device ID
All zeros
Parity error
response
Description
6
Description
5
—
3
Bus master
2
Register—0x54,” and the
Freescale Semiconductor
Memory
space
Access: Read only
1
Access: Mixed
I/O space
0
0