MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 693

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.4.2.2
The basic GPCM write timing parameters that may be set by the ORn attributes are shown in
The write access cycle commences upon latching of the memory address (LALE negated), and concludes
when LCSn returns high. LBCTL remains stable for the entire cycle to drive data onto any secondary data
bus. Write data becomes invalid following the falling edge of TA. LWE may, in some cases, negate high
before the end of the write access to provide additional hold time for the external memory.
Freescale Semiconductor
TRLX
Option Register Attributes
1
1
1
1
1
1
1
1
1
1
LBCTL
GPCM Write Signal Timing
LCLK
LALE
LCS n
LWE
LAD
EHTR
TA
A
0
0
0
0
1
1
1
1
1
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Notes:
t
t
t
WC
AWCS
AWE
XACS
Table 13-32. GPCM Read Control Signal Timing (continued)
= Write cycle time.
= Address valid to write enable time.
Address
0
1
1
1
0
0
0
1
1
1
= Address valid to write chip-select time.
Figure 13-37. GPCM General Write Timing Parameters
ACS
0X
0X
0X
11
10
11
10
11
10
11
t
AWCS
t
ARCS
1½
1¼
1½
t
AWE
0
2
3
0
0
2
3
1½+2×SCY
1¾+2×SCY
1½+2×SCY
2+2×SCY
1+2×SCY
1+2×SCY
2+2×SCY
2+2×SCY
1+2×SCY
1+2×SCY
Signal Timing (LCLK clock cycles)
t
Write Data
Latched Address
CSRP
t
t
t
WC
CSWP
WEN
t
CSWP
= Write enable negated time wrt chip-selec
= Write chip-select assertion period.
t
AOE
2
1
2
3
1
2
2
1
2
3
t
WEN
t
OEN
4
4
4
4
8
8
8
8
8
8
Enhanced Local Bus Controller
10+2×SCY
11+2×SCY
11+2×SCY
10+2×SCY
11+2×SCY
12+2×SCY
7+2×SCY
6+2×SCY
7+2×SCY
8+2×SCY
t
RC
Figure
13-37.
13-51