MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1101

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Port
rates of 527 MHz or greater.
Table 17-2
17.3
The PCI Express interface supports the following register types:
Freescale Semiconductor
SD1_RX[7:0]
SD1_RX[7:0]
SD1_TX[7:0]
SD1_TX[7:0]
•
•
Signal
Selection,” for specific pin muxing details. Note that the x8 link width is only available at CCB clock
Memory-mapped registers—these registers control PCI Express address translation, PCI error
management, and PCI Express configuration register access. These registers are described in
Section 17.3.1, “PCI Express Memory Mapped Registers,”
PCI Express configuration registers contained within the PCI Express configuration space—these
registers are specified by the PCI Express specification for every PCI Express device. These
registers are described in
subsections.
Memory Map/Register Definitions
contains detailed descriptions of the external PCI Express interface signals.
I/O
O
O
I
I
Table 17-2. PCI Express Interface Signals—Detailed Signal Descriptions
Receive data. The receive data signals carry PCI Express packet information. PCI Express signals may
appear as follows:
PCI Express 3: SD1_RX[7:6]
Receive data, inverted. SD1_RX[7:0]are the inverted forms of the receive data signals (SD1_RX[7:0]).
Transmit data. The transmit data signals carry PCI Express packet information. PCI Express signals may
appear as follows:
PCI Express 3: SD1_RX[7:6]
Transmit data, inverted. SD1_TX[7:0] are the inverted form of the transmit data signals (SD1_TX[7:0]).
• PCI Express 1: SD1_RX[7:0] or SD1_RX[3:0]
• PCI Express 2: SD1_RX[7:4] or SD1_RX[5:4]
Meaning
Meaning
• PCI Express 1: SD1_RX[7:0] or SD1_RX[3:0]
• PCI Express 2: SD1_RX[7:4] or SD1_RX[5:4]
Meaning
Meaning
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Timing Assertion/Negation—As described in the PCI Express Base Specification, Revision 1.0a .
Timing Assertion/Negation—As described in the PCI Express Base Specification, Revision 1.0a .
Timing Assertion/Negation—As described in the PCI Express Base Specification, Revision 1.0a .
Timing Assertion/Negation—As described in the PCI Express Base Specification, Revision 1.0a .
State
State
State
State
Asserted/Negated—Represents data being received from the PCI Express interface.
Asserted/Negated—Represents the inverse of data being received from the PCI Express
interface.
Asserted/Negated—Represents data being transmitted to the PCI Express interface.
Asserted/Negated—Represents the inverse of data being transmitted to the PCI Express
interface.
Section 17.3.7, “PCI Express Configuration Space Access,”
Description
and its subsections.
PCI Express Interface Controller
and its
17-5