MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 877

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14-122
14.5.3.11.8 Timer Drift Compensation Addend Register (TMR_ADD)
Timer drift compensation addend register (TMR_ADD) is used to hold timer frequency compensation
value (FreqCompensationValue). The nominal frequency of the clock counter is determined by the
FreqDivRatio and the clock frequency (FreqClock). This register is programmed with 2
Frequency division ratio (FreqDivRatio) is the ratio between the frequency of the oscillator (TimerOsc)
and the desired clock frequency (NominalFreq). FreqDivRatio is a design constant chosen to be greater
than 1.0001. The ADDEND value is added to the 32-bit accumulator register at every rising edge of the
oscillator clock (TimerOsc). The clock counter is incremented at every carry pulse of the accumulator.
Only one of this register is required for the entire group of eTSECs. Figure 14-115 describes the definition
of the TMR_ADD register.
Freescale Semiconductor
Offset eTSEC1:0x2_4E18 (H); 0x2_4E1C (L)
Reset
0–63
Bits
W
R
Offset eTSEC1:0x2_4E20
Reset
0
W
R
TMR_CNT_
0
Name
H/L
describes the fields of the TMR_CNT_H/L register.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Value of the current time counter. Current time is calculated by adding TMROFF_H/L with the
TMR_CNT_H/L counter. This register can be written through the register writes.Writes to the
TMR_CNT_L register copies the written value into the shadow TMR_CNT_L register. Writes to the
TMR_CNT_H register copies the values written into the shadow TMR_CNT_H register. Contents of the
shadow registers are copied into the TMR_CNT_L and TMR_CNT_H registers following a write into
the TMR_CNT_H register. Writes to these registers have precedence over the timer increment. The
user must write to TMR_CNT_L register first.
Reads from the TMR_CNT_L register copies the entire 64-bit clock time of the read enable into the
TMR_CNT_H/L shadow registers. Read instruction from the TMR_CNT_H register reads the value
stored in the TMR_CNT_H shadow register. The user must read the TMR_CNT_L register first to get
correct 64-bit TMR_CNT_H/L counter values.
TMR_CNT_H
Table 14-122. TMR_CNT_H/L Register Field Descriptions
Figure 14-114. TMR_CNT_H Register Definition
Figure 14-115. TMR_ADD Register Definition
ADDEND
All zeros
All zeros
31 32
Description
Enhanced Three-Speed Ethernet Controllers
TMR_CNT_L
Access: Read/Write
32
Access: Read/Write
/FreqDivRatio.
31
14-129
63