MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 55

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure
Number
1-1
1-2
1-3
1-4
1-5
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
5-1
5-2
6-1
6-2
6-3
6-4
6-5
6-6
Freescale Semiconductor
MPC8536E Block Diagram .................................................................................................... 1-2
Multi-Function Printer Application ...................................................................................... 1-11
Network Attached Storage Application ................................................................................ 1-12
Gaming Kiosk Application ................................................................................................... 1-13
Network Controller Application ........................................................................................... 1-14
Local Memory Map Example ................................................................................................. 2-2
Local Access IP Block Revision Register 1 (LAIPBRR1) ..................................................... 2-6
Local Access IP Block Revision Register 2 (LAIPBRR2) ..................................................... 2-6
Local Access Window n Base Address Registers (LAWBAR0–LAWBAR7) ....................... 2-7
Local Access Window n Attributes Registers (LAWAR0–LAWAR7) ................................... 2-7
General Utilities Registers Mapping to Configuration, Control,
PIC Mapping to Configuration, Control, and Status Memory Block ................................... 2-13
Device-Specific Register Mapping to Configuration, Control,
Configuration, Control, and Status Registers Base Address Register (CCSRBAR) .............. 4-5
Alternate Configuration Base Address Register (ALTCBAR) ............................................... 4-6
Alternate Configuration Attribute Register (ALTCAR) ......................................................... 4-6
Boot Page Translation Register (BPTR) ................................................................................. 4-7
Power-On Reset Sequence .................................................................................................... 4-10
Clock Subsystem Block Diagram ......................................................................................... 4-25
RTC and Core Timer Facilities Clocking Options ................................................................ 4-27
SD/MMC Card Data Structure.............................................................................................. 4-29
Config Address Fields........................................................................................................... 4-31
SD/MMC Card Data Structure for Maximum Redundancy ................................................. 4-35
eSPI EEPROM Data Structure.............................................................................................. 4-37
Config Address Fields........................................................................................................... 4-39
External Signal Connection .................................................................................................. 4-40
eSPI CS0 Mode Register (SPMODE0) Configuration ......................................................... 4-40
Read Instruction Timing Diagram (24-bit addressable eSPI memory)................................. 4-41
e500 Core Complex Block Diagram ....................................................................................... 5-2
e500 Core Integration.............................................................................................................. 5-3
L2 Cache/SRAM Configuration ............................................................................................. 6-1
Cache Organization ................................................................................................................. 6-4
Physical Address Usage for L2 Cache Accesses .................................................................... 6-5
Physical Address Usage for SRAM Accesses ........................................................................ 6-6
Data Bus Connection of CCB ................................................................................................. 6-8
Address Bus Connection of CCB............................................................................................ 6-8
and Status Memory Block ................................................................................................ 2-12
and Status Memory Block ................................................................................................ 2-14
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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