MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 72

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure
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17-31
17-32
17-33
17-34
17-35
17-36
17-37
17-38
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17-40
17-41
17-42
17-43
17-44
17-45
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17-50
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17-56
17-57
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17-59
17-60
17-61
17-62
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17-66
lxxii
PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1)
PCI Express Error Capture Register 2 (PEX_ERR_CAP_R2)
PCI Express Error Capture Register 2 (PEX_ERR_CAP_R2)
PCI Express Error Capture Register 3 (PEX_ERR_CAP_R3)
PCI Express Error Capture Register 3 (PEX_ERR_CAP_R3)
PCI Express PCI-Compatible Configuration Header Common Registers.......................... 17-45
PCI Express Vendor ID Register......................................................................................... 17-45
PCI Express Device ID Register ......................................................................................... 17-46
PCI Express Command Register......................................................................................... 17-46
PCI Express Status Register................................................................................................ 17-47
PCI Express Revision ID Register ...................................................................................... 17-48
PCI Express Class Code Register ....................................................................................... 17-49
PCI Express Bus Cache Line Size Register ........................................................................ 17-49
PCI Express Bus Latency Timer Register........................................................................... 17-50
PCI Express Bus Latency Timer Register........................................................................... 17-50
PCI Express PCI-Compatible Configuration Header—Type 0........................................... 17-51
PCI Express Base Address Register 0 (PEXCSRBAR)...................................................... 17-52
32-Bit Memory Base Address Register (BAR1)................................................................. 17-52
64-Bit Low Memory Base Address Register ...................................................................... 17-53
64-Bit High Memory Base Address Register ..................................................................... 17-53
PCI Express Subsystem Vendor ID Register ...................................................................... 17-54
PCI Express Subsystem ID Register ................................................................................... 17-54
Capabilities Pointer Register............................................................................................... 17-55
PCI Express Interrupt Line Register ................................................................................... 17-55
PCI Express Interrupt Pin Register ..................................................................................... 17-56
PCI Express Maximum Grant Register (MAX_GNT) ....................................................... 17-56
PCI Express Maximum Latency Register (MAX_LAT)..................................................... 17-57
PCI Express PCI-Compatible Configuration Header—Type 1........................................... 17-57
PCI Express Base Address Register 0 (PEXCSRBAR)...................................................... 17-58
PCI Express Primary Bus Number Register ....................................................................... 17-58
PCI Express Secondary Bus Number Register ................................................................... 17-59
PCI Express Subordinate Bus Number Register................................................................. 17-59
PCI Express I/O Base Register ........................................................................................... 17-60
PCI Express I/O Limit Register .......................................................................................... 17-60
PCI Express Secondary Status Register.............................................................................. 17-61
PCI Express Memory Base Register ................................................................................... 17-62
External Source, Inbound Transaction ........................................................................... 17-39
Internal Source, Outbound Transaction.......................................................................... 17-40
External Source, Inbound Transaction ........................................................................... 17-41
Internal Source, Outbound Transaction.......................................................................... 17-42
External Source, Inbound Transaction ........................................................................... 17-42
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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