MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1099

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

controller performs PCI Express ordering rule checking to determine which transaction is to be sent on the
PCI Express link.
In general, transactions are serviced in the order that they are received from the internal platform (OCeaN).
Only when there is a stalled condition does the controller apply PCI Express ordering rules to outstanding
transactions. For posted write transactions, once all data has been received from the internal platform
(OCeaN), the data is forwarded to the PCI Express link and the transaction is considered as done. For
non-posted write transactions, the controller waits for the completion packets to return before considering
the transaction finished. For non-posted read transactions, the controller waits for all completion packets
to return and then forwards all data back to the internal platform before terminating the transaction.
Note that after reset or when recovering from a link down condition, external transactions should not be
attempted until the link has successfully trained. Software can poll the LTSSM state status register
(PEX_LTSSM_STAT) to check the status of link training before issuing external requests.
17.1.1.2
Inbound PCI Express transactions to internal platform are first mapped to a translation window to
determine what internal platform transactions are to be issued.
A transaction may be broken up into smaller sized transactions when sending to the internal platform
depending on the original request size, byte enables and starting/ending addresses. The controller performs
PCI Express ordering rule checking to determine what transaction is to be sent next to the internal platform
(OCeaN).
In general, transactions are serviced in the order that they are received from the PCI Express link. Only
when there is a stalled condition does the controller apply PCI Express ordering to outstanding
transactions. For posted write transactions, once all data has been received from the PCI Express link, the
data is forwarded to the internal platform and the transaction is considered as done. For non-posted read
transactions, the controller forwards internal platform data back to the PCI Express link.
Note that the controller splits transactions at the crossing of every 256-byte-aligned boundary when
sending data back to the PCI Express link.
17.1.2
The following is a list of features supported by the PCI Express controller:
Freescale Semiconductor
•
•
•
•
•
•
•
•
Compatible with the PCI Express™ Base Specification, Revision 1.0a
Supports root complex (RC) and endpoint (EP) configurations
32- and 64-bit address support
x8, x4, x2, and x1 link support. (x8 link width only available at CCB clock rates of 527 MHz or
greater)
Supports accesses to all PCI Express memory and I/O address spaces (requestor only)
Supports posting of processor-to-PCI Express and PCI Express-to-memory writes
Supports strong and relaxed transaction ordering rules
PCI Express configuration registers (type 0 in EP mode, type 1 in RC mode)
Features
Inbound Transactions
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
PCI Express Interface Controller
17-3