MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1077
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MPC8536E-ANDROID
Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr
Datasheets
1.MPC8536EBVTAVLA.pdf
(127 pages)
2.MPC8536EBVTAVLA.pdf
(2 pages)
3.MPC8536EBVTAVLA.pdf
(1706 pages)
Specifications of MPC8536E-ANDROID
Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 16-49
Figure 16-50
16.4.2.7.2
This section describes PCI single-beat write transactions, and PCI burst write transactions. A PCI write
transaction starts with the address phase, occurring when an initiator asserts PCI_FRAME. A write
transaction is similar to a read transaction except no turnaround cycle is needed following the address
phase because the initiator provides both address and data. The data phases are the same for both read and
write transactions. Although not shown in the figures, the initiator must drive the PCI_C/BE[3:0] signals,
even if the initiator is not ready to provide valid data (PCI_IRDY negated).
Freescale Semiconductor
PCI_DEVSEL
PCI_DEVSEL
PCI_FRAME
PCI_FRAME
PCI_TRDY
PCI_TRDY
PCI_C/BE
PCI_IRDY
PCI_C/BE
PCI_IRDY
illustrates a PCI single-beat read transaction.
illustrates a PCI burst read transaction.
SYSCLK
SYSCLK
PCI_AD
PCI_AD
PCI Write Transactions
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 16-49. PCI Single-Beat Read Transaction
ADDR
ADDR
CMD
CMD
Figure 16-50. PCI Burst Read Transaction
Byte Enables 1
DATA1
Byte Enables
Byte Enables 2
DATA2
DATA
PCI Bus Interface
16-51
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