MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 396

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0–29
Programmable Interrupt Controller (PIC)
Table 9-16
9.3.2.5
The GTDRxn registers, shown in
is directed. Note that GTDRxn bits can be set independently of each other and that either P1 or P0 or both
can be set for this type of interrupt.
Table 9-17
Bits Name
9-26
12–15 PRIORITY Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A priority level
16–31 VECTOR Vector (Affects only interrupts routed to int ). Contains the value returned when IACK is read and this interrupt
Offset Group A: GDTRA0: 0x1130; GDTRA1: 0x1170; GDTRA2: 0x11B0; GDTRA3: 0x11F0;
Reset 0
30
31
2–11
Bits
0
1
W
R
Group B: GDTRB0: 0x2130; GDTRB1: 0x2170; GDTRB2: 0x21B0; GDTRB3: 0x21F0
1
P1
P0
—
0
Reserved in single-processor implementations.
Name
MSK
0
—
A
describes the GTVPRxn fields.
describes the GTDRxn fields.
Reserved, should be cleared.
Processor core 1. This interrupt is multicasting, so both P0 and P1 can be set.
0 Processor core 1 does not receive this interrupt
1 Directs the timer interrupt to processor core 1
Note: Reserved in single-processor implementations.
Processor core 0. Default destination after PIC is reset. Both P0 and P1 can be set.
0 Processor core 0 does not receive this interrupt.
1 Directs the timer interrupt to processor core 0.
0
Global Timer Destination Registers (GTDRA0–GTDRA3,
GTDRB0–GTDRB3)
0
Mask. Mask interrupts to int from this source.
0 An interrupt request is generated if the corresponding IPR bit is set.
1 Further interrupts from this source are disabled.
Activity. Indicates an interrupt has been requested or is in service. The VECTOR and PRIORITY values
should not be changed while this bit is set.
0 No current interrupt activity associated with this source.
1 The interrupt field for this source is set in the IPR or ISR.
Reserved, should be cleared.
of 0 inhibits signalling of this interrupt to the core. Affects only interrupts routed to int .
resides in the corresponding interrupt request register (IRR) for that core, as shown in
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
Figure 9-15. Global Timer Destination Registers (GTDR xn )
0
0
0
Figure
Table 9-16. GTVPR xn Field Descriptions
Table 9-17. GTDR xn Field Descriptions
0
0
9-15, control the destination (core) to which each timer’s interrupt
0
0
0
0
—
0
Description
Description
0
0
0
0
0
0
0
0
0
0
Freescale Semiconductor
0
Figure
0
0
9-50.
29
Read/Write
0
P1
Access:
30
0
1
P0
31
1