MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1228

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Serial Peripheral Interface
Figure 18-19
transfer (SPMODEx[CPx] = 1).
18.3.1.8
1) Regular devices - eSPI mode0 - CI=CP=0
2) Regular devices - eSPI mode3 - CI=CP=1
For Winbond devices DO should also be set for dual output read command.
3) RapidS mode0 - CI=0, CP=1, HLD = 1
4) RapidS mode3 - CI=1, CP=0
18.4
18.4.1
The following sequence initializes the eSPI to read 36 bytes from 24-bit address memory, start
address = 0x00_0040:
18-14
1. Configure a parallel I/O signal to operate as the eSPI CS1 output signal.
2. Write 0xFFFF_FFFF to SPIE to clear any previous events. Configure SPIM to enable all desired
3. Configure SPMODE=0x8000_100F to enable normal operation, eSPI enabled.
4. Configure SPMODE1=0x2417_1108—REV1=1, PM1=4 (divide eSPI input clock by 10) , LEN1
5. Configure SPCOM=0x0004_0027 so 4 bytes are skipped (1 for opcode and 3 for 24-bit address),
6. Configure SPITF=0x0300_0040—0x03 is read opcode while 0x000040 is the 24-bit start address.
(From Master)
eSPI interrupts.
= 7, POL1=1, CS1BEF=CS1AFT=CS1CG=1.
TRANLEN= 36+4–1.
(From Slave)
CSx/SPISEL
eSPI Programming Examples
SPI_MOSI
SPI_MISO
SPI_CLK
24-bit Address Example
SPI_CLK
CI and CP Values for Various eSPI Devices
shows the eSPI transfer format in which SPI_CLK starts toggling at the beginning of the
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
NOTE: Q = Undefined Signal.
(CI = 0)
(CI = 1)
Figure 18-19. eSPI Transfer Format with SPMODEx[CPx] = 1
Q
msb
msb
lsb
Freescale Semiconductor
lsb