MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1538

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MPC8536E-ANDROID

Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr

Specifications of MPC8536E-ANDROID

Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Global Utilities
23-46
14–15
18–23 SDTXLA Controls lane A transmitter amplitude levels.
16-17
Bits
SDFME Sets the bandwidth of the digital filter to optimize for given frequency offset specification for lane E.
Name
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
00 200 ppm (SGMII)
01 600 ppm (SATA)
10 Reserved
11 Reserved
Recommended setting per protocol:
Reserved
If SRDS2CR0[19] = 0, then Full Swing = Vdd/2 and bit settings are as follows:
bits [18–20] = Reserved
000 No amplitude reduction
001 0.916
010 0.833
011 0.750
100 0.666
101 0.583
110 0.500
111 Reserved
If SRDS2CR0[19] = 1, then Full Swing = 5/6 * Vdd/2 and bit settings are as follows:
bits [18–20] = Reserved
000 No amplitude reduction
001 0.916
010 0.833
011 0.750
100 0.666
101 0.583
110 0.500
111 Reserved
Recommended setting per protocol:
• SGMII: 00
• SATA: 01
• SGMII: 000
• SATA: 101
Table 23-36. SRDS2CR3 Field Descriptions (continued)
full swing
full swing
full swing
full swing
full swing
full swing
full swing
full swing
full swing
full swing
full swing
full swing
Description
Freescale Semiconductor

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