MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1544

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
During the Jog mode process, ASLEEP is asserted and READY is negated. When the Jog sequence
completes and the system resumes operation, ASLEEP is negated and READY is asserted.
23.5.1.7
The e500 core provides the following fields to signal power management requests to the MPC8536E
device logic:
These register fields and their functional relationship are shown in
Family Reference Manual has details on accessing these power management control bits. An external
master can also initiate power management requests by setting the DOZ, SLP or DPSLP bits in the
memory-mapped power management control and status register (POWMGTCSR). Because the core
responds to snoops while dozing but not while napping, maintaining cache coherency requires significant
preparation by the core before entering nap mode. For this reason only the core can initiate a nap during
normal operation while other masters can initiate a doze.
23-52
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MSR[WE] Used to qualify the values of HID0[DOZE,NAP,SLEEP] in the generation of the
internal doze, nap, and sleep signals.
HID0[DOZE] Signals the MPC8536E to initiate doze mode.
HID0[NAP] Signals the MPC8536E to initiate nap mode.
HID0[SLEEP] Signals the MPC8536E to initiate sleep mode.
Power Management Control Fields (e500)
The user must not issue a jog request at the same time as issuing a request
for another low power mode, or while the system is in the process of
entering a low power mode. The user also must not enter another low power
mode when performing a jog sequence.
In other words, POWMGTCSR[JOG] must never be set simultaneously
with any other fields of POWMGTCSR.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
NOTE
Figure
23-35. The PowerPC e500 Core
Freescale Semiconductor