MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1702

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S–S
Index-16
performance monitor, descriptions, 24-3
PIC, 9-19
PKEU
PKEU data size, 10-149
processor version register (PVR), 23-29
RNG
security engine (SEC)
system version register (SVR), 23-30
trace buffer, 25-15–25-22
trigger out source register, 25-23
USB interface, 21-6–??
memory-mapped registers
global registers, 9-19–9-23
global timer registers, 9-23–9-28
interrupt source configuration registers, 9-24–9-26,
message registers, 9-34–??
non-accessible registers
per-CPU registers, 9-46–9-51
performance monitor mask registers, 9-32–9-34,
summary registers, 9-28–??, 9-28–9-32, ??–9-32
EU_GO, 10-96, 10-116, 10-143, 10-154, 10-160
interrupt control, 10-153
interrupt status, 10-151
key size, 10-147, 10-148
reset control, 10-149
status, 10-112, 10-150
data size, 10-156
interrupt control, 10-159
interrupt status, 10-158
mode, 10-156
reset control, 10-156
KEU, 10-118–??
configuration and status register base address
device ID register, 16-31, 16-39
interrupt line register, 16-39
interrupt pin register, 16-40
latency timer register, 16-36
maximum grant (MAX GNT) register, 16-40
maximum latency (MAX LAT) register, 16-41
programming interface register, 16-34
revision ID register, 16-34
subclass code register, 16-35
vendor ID, 16-30, 16-38
ATMU inbound registers, 16-19–16-23
ATMU outbound registers, 16-15–16-19
configuration access registers, 16-14–16-15, 16-60
error management registers, 16-23–16-29
interrupt pending register (IPR), 9-52
interrupt request register (IRR), 9-53
9-40–??
??–9-34
(PCSRBAR), 16-36
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
registers
Reset
RMON support, see eTSEC, modes of operation
RNG
RTC (real time clock) signal, 4-3, 4-26, 9-27, 9-28
RTS, see DUART_RTS[0:1]
S
SCL (I
SD_RX[7:0]/SD_RX[7:0] (PCI Express serial data input and
SD_TX[7:0]/SD_TX[7:0] (PCI Express serial data output
SDA (I
Security engine (SEC)
Serial data/clock, see I
Serial peripheral interface (SPI)
Signals
watchpoint monitor, 25-10–25-15
SPI command,, 18-9
SPI event,, 18-6, 18-7
SPI mode,, 18-6, 18-12
core reset through PIC register, 9-22, 9-58
hard reset actions, 4-8
HRESET_REQ control, 23-30
operations, 4-8
power-on reset (POR)
requests from RapidIO and PCI Express, 23-28
signals summary, 4-2
soft request, 23-27, 23-28
soft reset actions, 4-8
data size register, 10-156
FIFO, 10-161
interrupt control register, 10-159
interrupt status register, 10-158
mode register, 10-156
reset control register, 10-156
register descriptions
multi-master operation, 18-3
clock
complete signal listing
capability registers, 21-6–21-10
operational registers, 21-10
configuration, see Power-on reset (POR), configuration
sequence of events, 4-9
see also Signals, reset
and reconfiguring the eTSEC, 14-161
complement) signals, 17-5
and complement) signals, 17-5
KEU, 10-118–??
RTC (real time clock), 4-3, 4-26, 9-27, 9-28
SYSCLK (system clock input), 4-3
alphabetical reference, 3-9
configuration signals, sampled at POR, 3-15
2
2
C serial clock) signal, 11-3, 11-4
C serial data) signal, 11-3, 11-4
2
C interface, 11-1
Freescale Semiconductor
Index