MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1533

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.4.1.31 SerDes2 Control Register 1 (SRDS2CR1)
Shown in
Individual lanes can be powered down using SRDS2CR1[0] and SRDS2CR1[4]. It requires the entire
SerDes2 to reset in order to activate a lane from powering down.
Table 23-34
Freescale Semiconductor
Offset 0xE_3104
Reset
Reset
Bits
1–3
5–7
W
W
R
R
0
4
8
9
PDA
16
0
0
—
Figure
17
0
1
describes the fields of SRDS2CR1.
IPSEN
Name
PDE
PDA
—
—
—
PPSEN
23-31, the SRDS2CR1 contains the functional control bits for the SerDes2 logic.
18
—
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Lane A power down
0) Normal
1) Power down Lane A
Recommended setting per protocol:
SGMII: 0
SATA: 0
Reserved
Lane E power down
0) Normal
1) Power down Lane E
Recommended setting per protocol:
SGMII: 0
SATA: 0
Reserved
Internal power save enable
0 SerDes power saving disabled
1 SerDes power saving enabled (recommended)
Reserved
19
0
3
Figure 23-31. SerDes2 Control Register 1 (SRDS2CR1)
PDE
20
0
4
Table 23-34. SRDS2CR1 Field Descriptions
21
0
5
—
0
0
7
IPSEN
24
0
8
All zeros
—
Description
25
1
9
—
X3SA
10
26
0
11
27
0
—
28
0
Access: Read/Write
13
29
0
Global Utilities
X3SE
14
30
0
23-41
—
15
31
0