MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 366

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
8-92
DLL_RST_DIS
RD_TO_PRE
FOUR_ACT
Parameter
DQS_CFG
CKE_PLS
RD_EN
2T_EN
8_BE
Table 8-69. Programming Differences Between Memory Types (continued)
Read to Precharge Timing
Minimum CKE Pulse Width DDR2
Four Activate Window
Registered DIMM Enable
8-beat burst enable
2T Timing Enable
DLL Reset Disable
DQS Configuration
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Description
DDR3
DDR3
DDR3
DDR3
DDR2
DDR3
DDR3
DDR3
DDR3
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
the memory used (t
precharge for non-zero value of additive latency
(AL) is a minimum of AL + t
the memory used (t
precharge for non-zero value of additive latency
(AL) is a minimum of AL + t
DDR_SDRAM_CFG_2[OBC_CFG] is set, then
this should be programmed to t
cycles.
the memory used (t
the memory used (t
the memory used (t
logical banks.
the memory used (t
should be set to 1
If registered DIMMs are used, then this field
should be set to 1
Should be set to 0
Otherwise, this should be set to 1. If this is set to
0, then other requirements in TIMING_CFG_4 is
needed to ensure t
gain extra timing margin on the interface at the
cost of address/command bandwidth.
gain extra timing margin on the interface at the
cost of address/command bandwidth.
bypass the DLL reset when exiting self refresh.
Should be set to 1
Should be set to 01
Should be set according to the specifications for
Should be set according to the specifications for
Should be set according to the specifications for
Should be set according to the specifications for
Should be set according to the specifications for
Should be set according to the specifications for
If registered DIMMs are used, then this field
If a 64-bit bus is used, this should be set to 0.
In heavily loaded systems, this can be set to 1 to
In heavily loaded systems, this can be set to 1 to
Should typically be set to 0, unless it is desired to
Should be set to 01
Differences
CCD
RTP
RTP
CKE
CKE
FAW
FAW
). Time between read and
). Time between read and
)
)
). Only applies to eight
).
is met.
RTP
RTP
RTP
cycles.
cycles. If
+ 2 DRAM
Freescale Semiconductor
Section/page
8.4.1.7/8-21
8.4.1.7/8-21
8.4.1.7/8-21
8.4.1.8/8-23
8.4.1.8/8-23
8.4.1.8/8-23
8.4.1.9/8-26
8.4.1.9/8-26