MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 110

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Part II, “e500 Core Complex and L2 Cache,” describes the integration of the e500v2 core in the
MPC8536E and the interaction between the core complex and the L2 cache. The following chapters are
included:
Part III, “Memory, Security, and I/O Interfaces,” defines the memory, security, and I/O interfaces of the
MPC8536E and how these blocks interact with one another and with other blocks on the device. The
following chapters are included:
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Chapter 5, “e500 Core Integration Details,”
how it is implemented in the MPC8536E.
Chapter 6, “L2 Look-Aside Cache/SRAM,”
the L2 cache can also be addressed directly as memory-mapped SRAM.
Chapter 7, “e500 Coherency Module,”
communication between the e500v2 core complex, the L2 cache, and the other blocks that
comprise the coherent memory domain of the MPC8536E.
The ECM provides a mechanism for I/O-initiated transactions to snoop the core complex bus
(CCB) of the e500v2 core in order to maintain coherency across cacheable local memory. It also
provides a flexible, easily expandable switch-type structure for e500v2- and I/O-initiated
transactions to be routed (dispatched) to target modules on the MPC8536E.
Chapter 8, “DDR Memory Controller,”
controllers of the MPC8536E. These fully programmable controllers support most DDR memories
available today, including both buffered and unbuffered devices. The built-in error checking and
correction (ECC) ensures very low bit-error rates for reliable high-frequency operation. Dynamic
power management and auto-precharge modes simplify memory system design. A large set of
special features like crawl mode and ECC error injection support rapid system debug.
Chapter 9, “Programmable Interrupt Controller (PIC),”
interrupt controller (PIC) of the MPC8536E. The PIC is an OpenPIC-compliant interrupt controller
that provides interrupt management and is responsible for receiving hardware-generated interrupts
from different sources (both internal and external), prioritizing them and delivering them to the
CPU for servicing.
Chapter 10, “Security Engine (SEC) 3.0,”
SEC 3.0 off-loads computationally intensive security functions, such as key generation and
exchange, authentication, and bulk encryption from the processor cores of the MPC8536E. It is
optimized to process all cryptographic algorithms associated with IPsec, IKE, SSL/TLS, iSCSI,
SRTP, 802.11i, 3G, A5/3 for GSM and EDGE, and GEA3 for GPRS.
Chapter 11, “I
This synchronous, serial, bidirectional, multi-master bus allows two-wire connection of devices,
such as microcontrollers, EEPROMs, real-time clock devices, A/D converters and LCDs. The
MPC8536E powers up in boot sequencer mode which allows the I
configuration registers.
Chapter 12, “DUART,”
(UARTs) which feature a PC16552D-compatible programming model. These independent UARTs
are provided specifically to support system debugging.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
C Interfaces,”
describes the (dual) universal asynchronous receiver/transmitters
describes the inter-IC (IIC or I
defines the e500v2 coherency module and how it facilitates
describes the two DDR2/DDR3 SDRAM memory
describes the security controller of the MPC8536E. The
provides an overview of the e500v2 core processor and
describes the L2 cache of the MPC8536E. Note that
describes the embedded programmable
2
C) bus controllers of the MPC8536E.
2
C1 controller to initialize
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