MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1143

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3.8.1.4
The status register, shown in
events.
Freescale Semiconductor
Offset 0x06
Reset
Reset
Bits
5–3
6
2
1
0
W
W
R
R
parity error
Bus master
Parity error
Detected
I/O space
response
Memory
Name
space
w1c
15
0
—
7
PCI Express Status Register—Offset 0x06
Table 17-39. PCI Express Command Register Field Descriptions (continued)
system error
Indicates whether this PCI Express device is configured as a master.
Controls whether this PCI Express controller responds to parity errors.
0 Parity errors are ignored and normal operation continues.
1 Parity errors cause the appropriate bit in the PCI Express status register to be set. However, note that
Note: The error control and status bits in the command and status registers control PCI-compatible error
Reserved
0 Disables the ability to generate PCI Express accesses
1 Enables this PCI Express controller to behave as a PCI Express bus master
EP mode: Clearing this bit prevent the device from issuing any memory or I/O transactions. Because MSI
interrupts are effectively memory writes, clearing this bit also disables the ability of the device to issue
MSI interrupts.
RC mode: Clearing this bit disables the ability of the device to forward memory transactions upstream.
This causes any inbound memory transaction to be treated as an unsupported request.
Controls whether this PCI Express device (as a target) responds to memory accesses.
0 This PCI Express device does not respond to PCI Express memory space accesses.
1 This PCI Express device responds to PCI Express memory space accesses.
EP mode: Clearing this bit prevents the device from accepting any memory transaction.
RC mode: This bit is ignored. It does not affect outbound memory transaction
I/O space.
0 This PCI Express device (as a target) does not respond to PCI Express I/O space accesses.
1 This PCI Express device (as a target) does respond to PCI Express I/O space accesses.
EP mode: Clearing this bit prevents the device from accepting any IO transaction. Note that this bit is a
RC mode: This bit is ignored. It does not affect outbound IO transaction.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Signaled
errors are reported based on the values set in the PCI Express error enable and detection registers.
don’t care in EP mode since the device does not support IO transaction.
w1c
—
14
0
reporting. PCI Express advanced error reporting is controlled by the PCI Express device control
register described in
advance error reporting capability structure described in sections 17.3.10.1 through 17.3.10.12.
Figure
master-abort
Figure 17-40. PCI Express Status Register
Received
w1c
13
17-40, is used to record status information for PCI Express related
0
5
Section 17.3.9.8, “PCI Express Device Control
target-abort
Capabilities
Received
w1c
list
12
4
1
All zeros
Description
target-abort
Signaled
Interrupt
Status
w1c
11
0
3
10
0
2
PCI Express Interface Controller
—
Register—0x54,” and the
—
0
9
Access: Mixed
Master data
parity error
w1c
0
8
0
17-47