MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 434

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
and SEC is the slave). Following the write, the channel directs the sequence of operations using the master
interface (where SEC is master). The channel uses the descriptor pointer to read the descriptor, then
decodes the first word of the descriptor to determine the operation to be performed and the
crypto-execution unit(s) needed to perform it (the execution units are introduced in
“Execution Units (EUs)
necessary, the channel waits for the needed crypto-execution unit(s) to be free. Next, the channel requests
the controller to transfer keys, context, and data from memory locations specified in the descriptor be sent
to the appropriate execution units. The controller satisfies the requests through its master interface. Data
is fed into the execution units through their registers and input FIFOs. The execution units read from their
input FIFOs and write processed data to their output FIFOs and registers. The channel requests the
controller to write data from the output FIFOs and registers back to system memory.
The channel can signal to the host that it is done with a descriptor by interrupt or by a writeback of the
descriptor header into host memory. For more about this signaling, see
Overview.”
Upon completion of a descriptor, the channel checks the next entry in its fetch FIFO, and (if non-empty)
requests a read of the next descriptor.
For most packets, the entire payload is too long to fit in an execution unit’s input or output FIFO, so the
channel uses a flow control scheme for reading and writing data. The channel directs the controller to read
bursts of input as necessary to keep refilling the input FIFO, until the entire payload has been fetched.
Similarly, the channel directs the controller to write bursts of output whenever enough accumulates in the
execution unit’s output FIFO.
The polychannel can process up to four descriptors concurrently by implementing the four virtual channels
(the polychannel is introduced in
Section 10.4,
execution unit is currently reserved by another channel. Each channel has its own FIFO of descriptor
pointers to fetch and execute, and its own internal storage. The four channels, however, time-share a single
control and datapath unit, and hence they are referred to as virtual channels. A programmable priority
scheme allows for round-robin or weighted priorities among these channels.
10.1.1
All of the SEC’s cryptographic functions are accessible through descriptors. This design facilitates easy
use and integration with existing systems and software.
A descriptor specifies cryptographic functions to be performed, and contains reference address pointers to
all necessary input data and to the locations where output data is to be written. Some descriptor types
perform multiple functions to facilitate particular protocols. A sample descriptor is diagrammed in
Table
10-4
•
10-1.Each descriptor contains eight dwords (64 bits each), consisting of the following:
One dword of header—The header describes the required services and encodes information that
indicates which EUs to use and which modes to set. It also indicates whether notification should
be sent to the host when the descriptor operation is complete.
Descriptor Overview
“Polychannel”). Channels arbitrate for use of execution units, and wait if the needed
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Overview,” and discussed in detail in
Section 10.1.2, “Polychannel
Section 10.7, “Execution
Overview,” and discussed in detail in
Section 10.1.2, “Polychannel
Section 10.1.4,
Freescale Semiconductor
Units”). If