MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1504

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
23.4.1.5
PORDBGMSR, shown in
described in
Configuration.”
Table 23-8
23-12
7–31
Offset 0x010
20–21
22–24
26–31
Reset 0 0 0 0 0
Bits
0–4
Bits
5
6
18
19
25
W
R
MEM_SEL Memory select. Indicates which controller is driving MSRCID[0:4] and MDVAL.
DDR_DBG DDR debug configuration
0
Name
CORE_SPD
—
—
RTYPE
describes the bit settings of PORDBGMSR.
Name
ECP3
—
Section 4.4.3.22, “Memory Debug Configuration,”
POR Debug Mode Status Register (PORDBGMSR)
—
—
—
Reserved
0 Local bus controller is driving debug information
1 DDR SDRAM controller is driving debug information
0 SourceID and data valid information is being driven on ECC pins of DDR SDRAM interface
1 Normal mode. ECC information is being driven on ECC pins of DDR SDRAM interface
Reserved
4
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
MEM_SEL DDR_DBG
Figure 23-5. POR Debug Mode Status Register (PORDBGMSR)
Core clock speed (See
This field reflects the current core speed, and therefore if this is changed by modifying
PMJCR[CORE_SPD] and executing a Deep Sleep or Jog request, then CORE_SPD may not
necessarily reflect the values at POR.
0 Core frequency at or below 800 MHz
1 Core frequency above 800 MHz
Reserved
eTSEC3 controller protocol (See
00 The eTSEC3 controller operates using the 8-bit FIFO protocol.
01 The eTSEC3 controller operates using the MII protocol (or RMII if configured in reduced mode).
10 The eTSEC3 controller operates using the RGMII protocol.
11 The eTSEC3 controller operates using the RTBI protocol .
Reserved
DRAM Type for DDR Controllers (See
0 DDR3 (1.5 V, CKE low at reset)
1 DDR2 (1.8 V, CKE low at reset)
Reserved
5
Table 23-7. PORDEVSR Field Descriptions (continued)
Figure
Table 23-8. PORDBGMSR Field Descriptions
23-5, holds debug mode settings from the POR configuration pins as
n
6
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7
Section 4.4.3.5, “Core Speed
Section 4.4.3.17, “eTSEC3
Section 4.4.3.12, “DDR SDRAM
Description
Description
and
Configuration”)
Section 4.4.3.23, “DDR Debug
—
Protocol.”)
Type.”)
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