MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 324

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
8.4.1.28
The DDRCDR_2, shown in
clocks driver P/N impedance.
Table 8-34
8.4.1.29
The DDR IP block revision 1 register, shown in
ID, along with major and minor revision information.
8-50
Offset 0xB2C
Reset
1
Offset 0xBF8
Reset n
For reset values, see
12–30
8–11
W
Bits
1–3
4–7
R
W
31
R
0
DSO_CLK_EN
0
1
n
describes the DDRCDR_2 fields.
0
DSO_CLK_EN
DSO_CLKNZ
DSO_CLKPZ
DDR Control Driver Register 2 (DDRCDR_2)
DDR IP Block Revision 1 (DDR_IP_REV1)
n
Name
n
ODT
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
n
1
Table 8-35
—
n
Figure 8-29. DDR Control Driver Register 2 (DDRCDR_2)
n
3
Figure 8-30. DDR IP Block Revision 1 (DDR_IP_REV1)
Figure
Reserved
Reserved
ODT termination value for IOs. This field is combined with DDRCDR_1[ODT] to determine
the termination value. Below is the termination based on concatenating these two fields.
000
001
010
011
100
101
110
111
Note that the order of concatenation is (from left to right)
Driver software override enable for clocks
Driver software clocks p-impedance override
Driver software clocks n-impedance override
IP_ID
n
4
.
DSO_CLKPZ
Table 8-34. DDRCDR_2 Field Descriptions
n
75
55
60
50
150
43
120
Reserved
DDRCDR_1[ODT], DDRCDR_2[ODT]
n
8-29, sets the driver software override enable for clocks, and the DDR
n
7
n
DSO_CLKNZ
8
n
n
Figure
n
11 12
All zeros
15 16
n
8-30, provides read-only fields with the IP block
n
n
Description
n
IP_MJ
n
n
n
n
—
23 24
n
n
Freescale Semiconductor
n
n
Access: Read/Write
Access: Read Only
IP_MN
n
n
n
30
n
ODT
31
31
n