MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 313

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4.1.20
The DDR ZQ Calibration Control register, shown in
for ZQ calibration when using DDR3 SDRAM devices.
There is a limitation for various DRAM timing parameters when ZQ calibration is used. The factors
involved in this limitation are DDR_ZQ_CNTL[ZQOPER], DDR_ZQ_CNTL[ZQCS],
TIMING_CFG_1[PRETOACT], TIMING_CFG_1[REFREC], DDR_SDRAM_INTERVAL[REFINT],
and the number of chip selects enabled. If the following condition is true:
then it is possible that one refresh is skipped when the controller is exiting self refresh. If this is an issue,
then posted refreshes could be used to extend the refresh interval. Another alternative is to use the
DDR_SDRAM_MD_CNTL register to force an extra refresh to each chip select after exiting self refresh
mode. However, DDR3 timing parameters for most devices/frequencies do not allow for a refresh to be
missed.
Table 8-26
Freescale Semiconductor
Offset 0x170
Reset
t
8–11
Bits
1–3
4–7
W
R
0
ZQ_EN
0
describes the DDR_ZQ_CNTL fields.
ZQ_EN
ZQINIT
DDR ZQ Calibration Control (DDR_ZQ_CNTL)
Name
[((DDR_ZQ_CNTL[ZQOPER] + DDR_ZQ_CNTL[ZQCS])* (# enabled chip selects)) +
TIMING_CFG_1[PRETOACT] +
TIMING_CFG_1[REFREC] + 2t
1
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 8-21. DDR ZQ Calibration Control Register (DDR_ZQ_CNTL)
3
4
ZQ Calibration Enable. This bit determines if ZQ calibration is used. This bit should only be set
if DDR3 memory is used (DDR_SDRAM_CFG[SDRAM_TYPE] = 3’b111).
0 ZQ Calibration is not used.
1 ZQ Calibration is used. A ZQCL command is issued by the DDR controller after POR and
Reserved, should be cleared.
POR ZQ Calibration Time (t
DRAM ZQ calibration at POR. Each chip select is calibrated separately, and this time must
elapse after the ZQCL command is issued for each chip select before a separate command may
be issued.
0000–0110 Reserved
0111 128 clocks
1000 256 clocks
1001 512 clocks
1010 1024 clocks
1011–1111 Reserved
Reserved, should be cleared.
ZQINIT
anytime the DDR controller is exiting self refresh. A ZQCS command is issued every 32
refresh sequences to account for VT variations.
Table 8-26. DDR_ZQ_CNTL Field Descriptions
7
8
—
11 12
ZQinit
CK
ZQOPER
] > (DDR_SDRAM_INTERVAL[REFINT]),
Figure
). Determines the number of cycles that must be allowed for
All zeros
15 16
Description
8-21, provides the enable and controls required
—
19 20
ZQCS
23 24
DDR Memory Controller
Access: Read/Write
—
8-39
31