MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 879

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset eTSEC1:0x2_4E40+8 n
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Table 14-125
14.5.3.11.11 Timer Offset Register (TMROFF_H/L)
The timer offset register is used to provide current time by adding its value to the clock counter. Figure
14-118 describes the definition of the TMROFF_H/L register.
Table 14-126
14.5.3.11.12 Alarm Time Comparator Register (TMR_ALARM1–2_H/L)
Alarm time comparator register (TMR_ALARMn_H/L). This register holds alarm time for comparison
with the current time counter. There are two of these registers for eTSEC1 which are shared amongst all
eTSECs. Figure 14-119 describes the definition for the TMR_ALARMn_H/L register.
Freescale Semiconductor
Offset eTSEC1:0x2_4E30 (H); 0x2_4E34 (L)
Reset
16–31
0–15
Bits
0–63
W
Bits
R
W
R
0
0
PRSC_OCK Output clock division/prescale factor. Output clock is generated by dividing the timer input clock by this
TMROFF_H/L Offset value of the clock counter. Current time in is calculated by adding TMROFF_H/L with the
Name
—
describes the fields of the TMR_PRSC register.
describes the fields of the TMROFF_H/L register.
Name
All TMROFF_H registers in a device should be set to the same value, and
all TMROFF_L registers in a device should be set to the same value.
Otherwise, the precision time protocol may not work.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
number. Programmed value in this field must be greater than 1. Any value less than 1 is treated as 2.
timer’s counter TMR_CNT_H/L register.
TMROFF_H
Table 14-126. TMROFF_H/L Register Field Descriptions
Figure 14-119. TMR_ALARM1-2_H/L Register Definition
ALARM_H
Table 14-125. TMR_PRSC Register Field Descriptions
Figure 14-118. TMROFF_H/L Register Definition
NOTE
All zeros
31 32
31 32
Description
Description
Enhanced Three-Speed Ethernet Controllers
TMROFF_L
ALARM_L
Access: Read/Write
Access: Read/Write
14-131
63
63