MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 866

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.5.3.9
This section describes the two eTSEC DMA attribute registers.
14.5.3.9.1
The attribute register defines memory access attributes and transaction types used to access buffer
descriptors, to write receive data, and to read transmit data. Snoop enable attributes may be set for reading
buffer descriptors and for reading transmit data. Buffer descriptors may be written with attributes that
cause allocation into the L2 cache. Similarly, broad sections of a receive frame header may have attributes
attached that cause allocation in the L2 cache. This process of specifying a region of each frame to stash
into the L2 cache is referred to as extraction, which is specified in conjunction with register ATTRELI.
ATTR[ELCWT] only has meaning if ATTRELI[EL] is non-zero. It is important to note that even though
portions of received frames may be stashed to L2 cache, this is only a performance optimization as entire
frames are still written to off-chip memory regardless of settings in ATTR.
Figure 14-106
14-118
30–31
Bits
26
27
28
29
Offset eTSEC1:0x2_4BF8;
Reset
W
R
CRCAPP Append a CRC (CRC-32 algorithm, as per IEEE Std. 802.3) to the end of every transmitted frame.
CRCCHK Check the CRC (CRC-32 algorithm, as per IEEE Std. 802.3) at the end of every frame.
eTSEC3:0x2_6BF8
0
Name
SIGM
FFC
—
DMA Attribute Registers
describes the definition for the ATTR register.
Attribute Register (ATTR)
Force flow control. This can be used by software to stop reception on the FIFO interface.
0 Do not assert link-level flow control through the RXFC signal unless eTSEC requires flow control.
1 Force flow control on the RXFC signal in encoded FIFO packet mode regardless of eTSEC pause
0 Do not automatically append a CRC to transmitted frames. Allow TxBD[TC], if set, to control when a
1 Automatically append a CRC to transmitted frames. Ignore TxBD[TC].
0 Do not automatically check the last 4 bytes of received frames for a valid CRC.
1 Automatically check the last 4 bytes of received frames for a valid CRC. If a CRC error is detected, or
Reserved
FIFO signaling mode. Determines how the GMII signals are interpreted as framing signals.
00 GMII style mode.
01 Encoded packet mode.
10 Reserved
11 Reserved
requirements.
CRC is appended.
insufficient data is received to recover the CRC, the RxBD[CR] bit is set.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 14-109. FIFOCFG Field Descriptions (continued)
—
Figure 14-106. ATTR Register Definition
16
ELCWT
17
18
All zeros
—
19
Description
BDLWT
20
21
22 23
—
RDSEN RBDSEN
24
25
Freescale Semiconductor
Access: Read/Write
26
—
31