MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1033

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
PCI_C/BE[3:0]
PCI_DEVSEL
PCI_FRAME
Signal
Table 16-2. PCI Interface Signals—Detailed Signal Descriptions (continued)
I/O
I/O Command/byte enable. The command/byte enable signals are both input and output signals on this
I/O Device select. The device select signal is both an input and output signal on this PCI controller.
I/O Frame. The frame signal is both an input and output signal on this PCI controller.
O As outputs for the bidirectional command/byte enable, these signals operate as described below.
O As outputs for the bidirectional device select, these signals operate as described below.
O As outputs for the bidirectional frame, these signals operate as described below.
I As inputs for the bidirectional command/byte enable, these signals operate as described below.
I As inputs for the bidirectional device select, these signals operate as described below.
I As inputs for the bidirectional frame, these signals operate as described below.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
PCI controller. The command encodings for PCI bus mode are described in
Commands.”
Meaning
Meaning
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
State
State
State
State
State
State
Asserted/Negated—During the address phase, PCI_C/BE[3:0] define the bus command.
Asserted/Negated—During the address phase, PCI_C/BE[3:0] indicate the command that
Asserted—Indicates that this PCI controller has decoded the address and is the target of
Negated—Indicates that this PCI controller has decoded the address and is not the target
Asserted—Indicates that some PCI agent (other than this PCI controller) has decoded its
Negated—Indicates that no PCI agent has been selected.
Asserted—Indicates that this PCI controller, acting as a PCI master, is initiating a bus
Negated—If PCI_IRDY is asserted, indicates that the PCI transaction is in the final data
Asserted—Indicates that another PCI master is initiating a bus transaction.
Negated—Indicates that the transaction is in the final data phase or that the bus is idle.
During the data phase, PCI_C/BE[3:0] act as byte enables indicating which byte lanes
carry meaningful data. The PCI_C/BE[0] signal applies to the LSB.
another master is sending. During the data phase, PCI_C/BE[3:0] indicate which byte
lanes are valid.
the current access.
of the current access.
address as the target of the current access.
transaction. While PCI_FRAME is asserted, data transfers may continue.
phase; if PCI_IRDY is negated, indicates that the PCI bus is idle.
Description
Section 16.4.2.2, “PCI Bus
PCI Bus Interface
16-7