MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 458

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
The construction and use of link tables is illustrated in
10-28
Length0 J=0
Length1 J=1
Length2 J=0 Extent2 Pointer2
Length3 J=1 Extent3 Pointer3
This figure illustrates various ways that a descriptor (table in upper left) may specify parcels:
The first pointer dword in the descriptor (following the header dword) specifies Parcel A using the simplest method—the
parcel is specified directly through Pointer0 and Length0.
The next pointer dword uses a chain of link tables to specify Parcel B. Since J=1, Pointer1 is used as the address of a link
table. The link table specifies several “regular” entries specifying data segments to be concatenated. The last word of the
link table is a “next” entry indicating that the list continues in the next link table. The last entry in the last link table of the chain
has the R bit set.
The last two cases illustrate how one pointer in a descriptor can be used to specify multiple parcels. Pointer2 and Length2
specify Parcel C, then Parcel D follows immediately afterwards, with length specified by Extent2. Pointer3 is used for three
parcels (E, F, and G), this time using link tables.
DESCRIPTOR
Header dword
Extent4
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Pointer0
Pointer1
Figure 10-6. Descriptors, Link Tables, and Parcels
LINKTABLES
N=1
N=1
R=1
N=1
R=1
Figure
10-6.
SEGMENTS
DATA
Freescale Semiconductor
PARCELS
Parcel C
Parcel D
Parcel G
Parcel A
Length0
Parcel B
Length1
Length2
Parcel E
Parcel F
Length3
Extent2
Extent3
Extent4
DATA