MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 524

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset 0x3_8038
Security Engine (SEC) 3.0
10.7.2.7
The interrupt mask register, shown in
(as defined in
is set, the error is disabled; no error interrupt occurs and the interrupt status register is not updated to reflect
the error. If the corresponding bit is not set, then upon detection of an error, the interrupt status register is
updated to reflect the error, causing assertion of the error interrupt signal, and causing the module to halt
processing.
Table 10-41
10-94
W
R
0
Bits
57
58
59
60
61
62
63
describes AFEU interrupt mask register fields.
AFEU Interrupt Mask Register
Section 10.7.2.6, “AFEU Interrupt Status
Names
OFU
OFE
IFO
IFE
AE
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-40. AFEU Interrupt Status Register Fields (continued)
—
Address Error. An illegal read or write address was detected within the AFEU address
space.
0 No error detected
1 Address error
Output FIFO Error. The AFEU output FIFO was detected non-empty upon write of
AFEU data size register.
0 No error detected
1 Output FIFO non-empty error
Input FIFO Error. The AFEU Input FIFO was detected non-empty upon generation of
done interrupt
0 Input FIFO non-empty error enabled
1 Input FIFO non-empty error disabled
Reserved
Input FIFO Overflow. The AFEU input FIFO was pushed while full.
1 Input FIFO has overflowed
0 No error detected
Note: When operated through channel-controlled access, the SEC implements flow
Output FIFO Underflow. The AFEU output FIFO was read while empty.
0 No error detected
1 Output FIFO has underflow error
Reserved
Figure 10-38. AFEU Interrupt Mask Register
control, which prevents input FIFO overflow—hence FIFO size is not a limit to
data input in this case. When operated through host-controlled access, the
AFEU cannot accept FIFO inputs larger than 256 bytes without overflowing.
Figure
10-38, controls the result of detected errors. For a given error
50 51
Register”), if the corresponding bit in this register
IE ERE CE KSE DSE ME AE OFE IFE — IFO OFU —
52
Description
53
54
55
56
57
Freescale Semiconductor
58
Access: Read/Write
59 60
61
62
63