MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 556

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
Table 10-57
10-126
0–48
Bits
49
50
51
52
53
54
55
56
57
58
59
60
61
Name
ERE
KSE
DSE
OFE
describes the KEU interrupt mask register fields.
ICE
IFO
IFE
CE
DE
AE
—
—
IE
—
Reserved
Integrity check error.
0 ICV check error enabled. WARNING: Do not enable this EU status writeback (see bits IWSE and
1 ICV check error disabled
Reserved
Internal error. An internal processing error was detected while performing encryption.
0 Internal error enabled
1 Internal error disabled
Early read error. A KEU context or IV register was read while the KEU was performing encryption.
0 Early read error enabled
1 Early read error disabled
Context error. A KEU key register, the key size register, data size register, mode register, or IV register
was modified while the KEU was performing encryption.
0 Context error enabled
1 Context error disabled
Key size error. An inappropriate value (not 16 or 32 bytes) was written to the KEU key size register.
0 Key size error enabled
1 Key size error disabled
Data size error. Indicates that the number of bits to process is out of range.
0 Data size error enabled
1 Data size error disabled
Data error. Indicates that invalid data was written to a register or a reserved mode bit was set.
0 Data error enabled
1 Data error disabled
Address error. An illegal read or write address was detected within the KEU address space.
0 Address error enabled
1 Address error disabled
Output FIFO error. The KEU output FIFO was detected non-empty upon write of the KEU data size
register.
0 Output FIFO non-empty error enabled
1 Output FIFO non-empty error disabled
Input FIFO error. The KEU input FIFO was detected non-empty upon generation of done interrupt.
0 Input FIFO non-empty error enabled
1 Input FIFO non-empty error disabled
Reserved
Input FIFO overflow. The KEU input FIFO was pushed while full.
0 Input FIFO overflow error enabled
1 Input FIFO overflow error disabled
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
AWSE in
Table 10-57. KEU Interrupt Mask Register Fields Description
Section 10.4.4.1, “Channel Configuration Register (CCR)”
Description
is used.
Freescale Semiconductor