MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1517

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 23-17
23.4.1.15 Power Management Clock Disable Register (PMCDR)
The power management clock disable register (PMCDR), shown in
various MPC8536E functional blocks. The register determines the blocks which will shut down the clock
in sleep/deep sleep power states.
Offset 0x08C
Freescale Semiconductor
Reset
Reset
16–31
8–15
W
W
Bits
0–2
3–7
R
R
16
0
0
PDCNT_PRE
PDCNT
describes PMPDCCR fields.
Name
0
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
Figure 23-15. Power Management Clock Disable Register (PMCDR)
Reserved
Power down count prescaler.
This field specifies the prescaler for the power down counter. Prescale value is 2
0x00 Reserved
0x01 1
0x02 2
0x03 4
0x04 8
...
0x08 128 (default)
...
0x1F 1,073,741,824
Power down count value.
This counter establishes a minimum time for which power can be removed to the VDD supply
during deep sleep. When the MPC8356E enters deep sleep the POWER_EN signal toggles low.
At this point this counter is loaded with the PDCNT value and begins to decrement at the rate
specified by the pre-scaler PDCNT_FDR. PMC will not respond to a wakeup request and toggle
POWER_EN high until this counter has expired. The count value is reloaded each time the VDD
power is removed. If POWMGCR1[DPSLP] = 0 this field has no effect. Software needs to set this
register based on the PMC clock frequency and the requirements of the power supply.
WARNING: If the value placed in this register is too small, the power supply may cycle too quickly
and the chip may not function properly.
The default values for PDCNT_PRE and PDCNT are set to provide a minimum of 50 s voltage
ramp-down time (when used with platform clock rates up to 533 MHz).
Reserved
19
0
Table 23-17. PMPDCCR Register Field Descriptions
—
SAP
20
1
21
0
—
0
23
0
7
All zeros
eTSEC1
USB1
24
0
8
Description
USB2
—
25
9
0
Figure
eTSEC3
USB3
10
26
0
23-15, contains bits to disable
11
27
0
28
0
Access: Read/Write
—
—
29
PDCNT_PRE–1
0
Global Utilities
30
0
23-25
.
15
31
0