MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 378

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller (PIC)
9.2.1
The PIC external interface signals are described in
request input signals and 1 interrupt request output signal IRQ_OUT. As
are also used for delivering INTx signals for the PCI Express root complexes.
9.2.2
Table 9-3
9-8
IRQ_OUT O Interrupt request out. When the PIC is programmed in pass-through mode, this output reflects the raw interrupts
IRQ[0:11]
Signal
MCP
I/O
provides detailed descriptions of the external PIC signals.
I Interrupt request 0–11. The polarity and sense of each of these signals is programmable. All of these inputs can
I Machine check processor. Assertion causes a machine check interrupt to the core. Note that if the core is not
Signal Overview
Detailed Signal Descriptions
be driven asynchronously.
Note: Some interrupt request signals IRQ n may share PIC external interrupt registers with PCI Express INTx
generated by on-chip sources. See
configured to process machine check interrupts (MSR[ME] = 0), assertion of MCP causes a core checkstop
condition. Note that internal sources for the internal core_mcp can also cause a machine check interrupt to the
processor core as described in
and
Meaning
Meaning
Meaning
Timing Assertion—All of these inputs can be asserted asynchronously.
Timing Because external interrupts are asynchronous with respect to the system clock, both assertion and
Timing Assertion—May occur at any time, asynchronous to any clock.
State
State
State
Table
signaling. See
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Asserted—When an external interrupt signal is asserted (according to the programmed polarity), the
Negated—There is no incoming interrupt from that source.
Negation—Interrupts programmed as level-sensitive must remain asserted until serviced. Timing
Asserted—At least one interrupt is currently being signalled to the external system.
Negated—Indicates no interrupt source currently routed to IRQ_OUT.
negation of IRQ_OUT occurs asynchronously with respect to the interrupt source. All timing given here
is approximate.
Assertion—Internal interrupt source: 2 CCB clock cycles after interrupt occurs.
Negation—Follows interrupt source negation with the following delay:
9-8.
Asserted—Integrated logic should direct the core to take a machine check interrupt or enter the
Negated—Machine check handling is not being requested by the external system.
Negation—Because MCP n is edge-triggered, it can be negated one clock after its assertion.
Table 9-3. Interrupt Signals—Detailed Signal Descriptions
PIC checks its priority and the interrupt is conditionally passed to the processor designated in the
corresponding destination register. In pass-through mode, only interrupts detected on IRQ0 are
passed directly to core 0.
requirements for edge-sensitive interrupts can be found in the Hardware Specifications .
External interrupt source: 4 cycles after interrupt occurs.
Message interrupts: 2 cycles after write to message register.
Internal interrupt: 2 CCB clock cycles
External interrupt: 4 cycles.
Message interrupts: 2 cycles after message register cleared.
checkstop state as directed by the MSR.
Section 9.4.5, “PCI Express INTx/IRQn Sharing.”
Section 17.4.1.12, “Machine Check Summary Register (MCPSUMR),” Table 9-1
Section 9.1.3, “Modes of
Table
Description
9-3. There are 12 distinct external interrupt
Operation.”
Table 9-3
shows, the IRQ inputs
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