MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1582

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Performance Monitor
3 and PMLCBn[TRIGOFFSEL] is 5, the counter begins and ends counting based on the conditions in
counters three and five. Furthermore, if PMLCBn[TRIGONCNTL] is 1, the counter begins counting when
PMC3 changes value. According to the setting in PMLCBn[TRIGOFFCNTL], the counter ends counting
when PMC5 overflows. Also, although the register settings for PMC5 is not shown, PMLCAn[CE] for this
counter must be cleared so that interrupt signalling is not enabled and the counter does not freeze when it
overflows.
For threshold counting, a threshold event must be specified in PMLCAn[EVENT]. For this example, the
duration threshold value is scaled by two because PMLCBn[TBMULT] is one. All other features are
disabled by clearing the appropriate fields.
Any non-threshold event can use the burstiness feature. For burstiness counting, values for
PMLCAn[BSIZE,BGRAN,BDIST] and PMLCBn[TBMULT] must be specified.
The performance monitor must be reset before event counting sequences. The performance monitor can
be reset by first freezing one or more counters and then clearing the freeze condition to allow the counters
to count according to the settings in the performance monitor registers. Counters can be frozen individually
by setting PMLCAn[FC] bits, or simultaneously by setting PMGC0[FAC]. Simply clearing these freeze
bits will then allow the performance monitor to begin counting based on the register settings.þ
Note that using PMLCAn[FC] to reset the performance monitor resets only the specified counter.
Performance monitor registers can be configured through reads or writes while the counters are frozen as
long as freeze bits are not cleared by the register accesses.
24-28
Register
PMLCA n
PMLCB n
PMGC0
TRIGOFFCNTL
Register Field
TRIGONCNTL
TRIGOFFSEL
THRESHOLD
TRIGONSEL
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
TBMULT
BGRAN
FCECE
EVENT
BDIST
BSIZE
PMIE
FAC
FC
CE
Table 24-12. Register Settings for Counting Examples
Simple Event
89
0
1
1
0
1
0
0
0
0
0
0
0
0
0
Triggering
68
0
1
1
0
1
0
0
0
3
5
1
2
0
0
Threshold
39
0
1
1
0
1
0
0
0
0
0
0
0
0
3
Freescale Semiconductor
Burstiness
0
1
1
0
1
2
5
1
8
0
0
0
0
0
0