MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 689

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.4.1.6
Parity can be configured for any GPCM or UPM bank by programming BRn[DECC]. Parity is generated
and checked on a per-byte basis using LDP[0:3] for the bank if BRn[DECC] = 01 (normal parity) or
BRn[DECC] = 10 for read-modify-write (RMW) parity. Byte lane parity on LDP[0:3] is generated
regardless of the BRn[DECC] setting. Note that RMW parity can be used only for 32-bit port size banks.
LBCR[EPAR] determines the global type of parity (odd or even).
FCM calculates an ECC over 512-byte blocks, and hence does not use the LDP[0:3] pins. The setting of
BRn[DECC] = 01 enables ECC checking only, while BRn[DECC] = 10 enables ECC generation and
checking; in either case, LBCR[EPAR] determines the global type of block parity for ECC (odd or even).
13.4.1.7
A bus monitor is provided to ensure that each bus cycle is terminated within a reasonable (user defined)
period. When a transaction starts, the bus monitor starts counting down from the time-out value
(LBCR[BMT] × LBCR[BMTPS]) until a data beat is acknowledged on the bus. It then reloads the time-out
value and resumes the countdown until the data tenure completes and then idles if there is no pending
transaction. Setting LTEDR[BMD] disables bus monitor error checking (i.e. the LTESR[BM] bit is not set
by a bus monitor time-out); however, the bus monitor is still active and can generate a UPM exception (as
noted in
It is very important to ensure that the value of LBCR[BMT] is not set too low; otherwise spurious bus
time-outs may occur during normal operation—resulting in incomplete data transfers. Accordingly, the
time-out value represented by the LBCR[BMT], LBCR[BMTPS] pair must not be set below 40 bus cycles
for time-out under any circumstances.
13.4.1.8
At LCLK frequencies in excess of 66 MHz the local bus PLL is used to provide improved hold times at
external receivers, and ease set-up margins for read data captured by eLBC. A wire loop between pins
LSYNC_OUT and LSYNC_IN establishes the amount of LCLK skewing achieved by the PLL, which
locks so as to produce edges on LCLK before the transition of other eLBC control and data signals.
At lower frequencies, the PLL may be unable to lock or provide sufficient hold time improvement for
particularly slow devices. Accordingly, LCRR[PBYP] should be set to 1 to bypass the PLL at low
frequencies, with the eLBC generating LCLK directly, while skewing it by half a bus clock cycle. An
illustration of GPCM or UPM timing both with and without the PLL activated are shown in
and
of the timing loop between LSYNC_OUT and LSYNC_IN, and data is generated or sampled on the next
rising edge of LCLK. The timing diagrams shown normally in this chapter assume that LCRR[PBYP] =
0. When LCRR[PBYP] = 1, the skew equals half the period of LCLK to maximize hold time at the external
receiver; in this bypass mode, eLBC drives new address, data, and control signals effectively on falling
Freescale Semiconductor
Figure
within 256 bus clock cycles, the reservation is released and an atomic error is reported (if enabled);
additional read transactions prior to the releasing write restart the reservation timer.
Section 13.4.4.1.4, “Exception
13-33. When LCRR[PBYP] = 0, the skew, t
Parity Generation and Checking (LDP)
Bus Monitor
PLL Bypass Mode
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Requests,”) or terminate a GPCM access.
LSKEW
, matches the round-trip propagation delay
Enhanced Local Bus Controller
Figure 13-32
13-47