MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1317

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.5.5
The clock generator generates the SDHC_CLK by dividing the internal bus clock into two stages. Refer
to
internal bus clock (ccb_clk/2). Refer to SYSCTL[SDCLKFS] and SYSCTL[DVS] (see
“System Control Register
The first stage is a prescaler. The frequency of clock output from this stage, DIV, can be base, base/2,
base/4, ..., or base/256.
The second stage outputs the actual clock, SDHC_CLK, as the driving clock for all sub-modules of SD
protocol unit, and the sync FIFOs in
buffer. It can be div, div/2, div/3,..., or div/16. Thus, the highest frequency of SDHC_CLK generated by
the internal bus clock (ccb_clk/2) is base while the lowest frequency is base/4096.
20.5.6
The eSDHC uses the SDHC_DAT[3] pin or the SDHC_CD pin to detect card insertion or removal. When
SDHC_DAT[3] pin is used for card detection, user needs to pull-down this pad as a default state. When
there is no card on the MMC/SD bus, the SDHC_DAT[3] is pulled to a low voltage level by default. When
any card is inserted to or removed from the socket, the eSDHC detects the logic value changes on the
SDHC_DAT[3] pin and generates an interrupt.
When SDHC_DAT[3] pin is not used for card detection, SDHC_CD must be connected for card detection.
It may be implemented by a GPIO. Whether SDHC_DAT[3] is configured for card detection or not,
SDHC_CD is always a reference for card detection, either SDHC_DAT[3] or SDHC_CD reports card
inserted, the eSDHC informs the host system that a card is inserted, and the interrupt is sent if it is enabled.
20.5.7
When there is no operation between eSDHC and the card through SD bus, you can completely disable the
internal clocks in the chip level clock control module to save power. When you need to use the eSDHC to
communicate with the card, it can enable the clock and start the operation. This can be done by clearing
the SCCR[SDHCCM] bits.
In some circumstances, when the clocks to eSDHC are disabled, or when system is in low power mode,
there are some events when you need to enable the clock and handle the event. These events are called
wakeup interrupts. The eSDHC can generate these interrupts even there are no clocks enabled. The three
interrupts which can be used as wake-up events are:
Freescale Semiconductor
Figure 20-24
•
•
Card removal interrupt
Card insertion interrupt
Clock Generator
Card Insertion and Removal Detection
Power Management and Wake-Up Events
Base
for the structure of the divider, in which the term base represents the frequency of the
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
(SYSCTL)”) to select the divisor values.
2, 4, . . . , 256
1st Divisor
Figure 20-24. Two Stages of Clock Divider
by
Figure 20-21
to synchronize with the data rate from the internal data
DIV
1, 2, 3, . . . , 16
2nd Divisor
by
Enhanced Secure Digital Host Controller
SDHC_CLK
Section 20.4.9,
20-43