MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1549

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

necessary configuration and control registers (CCSRs), and to disable the L2 Cache (L2CTL[L2E] = 0)
before issuing the command (writing to POWMGTCSR) to put the device into deep sleep. These steps are
necessary in order for the core to successfully re-boot on wake-up and reset from deep sleep. After
disabling the L2 Cache, either before or after deep sleep (but prior to re-enabling the L2 Cache), software
must also flash invalidate the L2 Cache (L2CTL[L2I] = 1). In addition to this, the requirements for
reaching and recovering from Sleep described above also must be met prior to entering deep sleep.
23.5.1.14 Requirements for Generating Wake-Up Events
The MPC8536E exits from low power modes based on a wake up interrupt from the OpenPIC. Any
interrupt connected to the OpenPIC can be configured by the e500 software to generate a wake up
interrupt.
23.5.1.14.1 USB
When the wake up event is generated to the USB host, it could be from the following reasons:
When the wake up event is generated to the USB device, it could be from the following reasons:
Refer also to
interrupt is connected to the OpenPIC to generate a wake up interrupt.
A USB interrupt can be generated either from the interrupt sources enabled by the USBINTR register, or
from the wake-up interrupt enabled by the CONTROL[WU_INT_EN] register field. When using wake up
from USB, software must clear the USBINTR register and set CONTROL[WU_INT_EN] to ensure that
the USB will only generate an interrupt due to a valid wake up event.
Prior to entering sleep or deep sleep, software for the USB host controllers needs to ensure that they are
idle by ensuring that USBCMD[ASE] = 0, USBCMD[PSE]=0, PORTSC[SUSP] = 1, and
USBCMD[RS] = 0. Software should then wait until USBSTS[HCH] = 1 before placing the system in
sleep or deep sleep modes. As described above, software also must clear the USBINTR register and set
CONTROL[WU_INT_EN].
Prior to entering sleep or deep sleep, software for the USB device controller also needs to ensure that it is
idle. Again, it must also must clear the USBINTR register and set CONTROL[WU_INT_EN].
When configured to wake on USB, the USB controller(s) interface to the off-chip USB PHY remains
operational in sleep or deep sleep, but the USB Controller will not initiate any traffic to DDR. The user
must set DDR_SDRAM_CFG[SREN] = 1 and optionally can also program DDR_SR_CNTR[SR_IT] to
a non-zero value.
Freescale Semiconductor
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Power fault
Disconnect
Connect
Remote Wakeup (resume signalling)
Resume signalling (USB not idle)
Section 21.6.4,
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
“Suspend/Resume,” for more details on USB wake up events. The USB
Global Utilities
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