MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1044
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MPC8536E-ANDROID
Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr
Datasheets
1.MPC8536EBVTAVLA.pdf
(127 pages)
2.MPC8536EBVTAVLA.pdf
(2 pages)
3.MPC8536EBVTAVLA.pdf
(1706 pages)
Specifications of MPC8536E-ANDROID
Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PCI Bus Interface
1
POWAR1–POWAR4 are shown in
Offset 0xC30, 0xC50, 0xC70, 0xC90
Reset
Table 16-10
16-18
Offset 0xC10
Reset 1
The default window is enabled, configured for memory read and memory write, and set to an OWS size of 4 Gbytes.
W
R
W
R
12–15
16–19
1–11
Bits
EN
EN
0
0
0
0
1
1
Figure 16-10. PCI Outbound Window 1–4 Attributes Registers (POWAR1–POWAR4)
Name
WTT
RTT
describes the fields for the POWARn registers.
EN
—
Figure 16-9. PCI Outbound Window 0 (Default) Attributes Register (POWAR0)
0 0 0 0 0 0 0 0 0
Enable. Enables this address translation
Reserved
Read transaction type to run on PCI
0000 Reserved
...
0011 Reserved
0100 Memory Read
0101 Reserved
...
0111 Reserved
1000 I/O Read
1001 Reserved
...
1111 Reserved
Write transaction type to run on PCI
0000 Reserved
...
0011 Reserved
0100 Memory Write
0101 Reserved
...
0111 Reserved
1000 I/O Write
1001 Reserved
...
1111 Reserved
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
—
Table 16-10. POWAR n Field Descriptions
Figure
11 12
0
16-10.
11 12
0
1
RTT
RTT
0
All zeros
15 16
0
15 16
Description
0
1
WTT
WTT
0
19 20
0
19 20
0
0
0
—
—
0
0
Freescale Semiconductor
25 26
0
25 26
0
Access: Read/Write
Access: Read/Write
1
OWS
1
OWS
1
1 1
31
31
1
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