MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 681

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MPC8536E-ANDROID

Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr

Specifications of MPC8536E-ANDROID

Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
13.3.1.20 Flash Block Address Register (FBAR)
Table 13-27
13.3.1.21 Flash Page Address Register (FPAR)
Freescale Semiconductor
Offset 0x0_50F0
Reset
Offset 0x0_50F0
Reset
Offset 0x0_50EC
Reset
The local bus Flash block address register (FBAR), shown in
block index for the page currently accessed.
The local bus Flash page address register (FPAR), shown in
current NAND Flash page in both the external NAND Flash device and FCM buffer RAM.
8–31
W
W
Bits
W
0–7
R
R
R
0
0
0
Name
BLK
describes FBAR fields.
Figure 13-26. Flash Page Address Register, Large Page Device (ORx[PGS] = 1)
Figure 13-25. Flash Page Address Register, Small Page Device (ORx[PGS] = 0)
Reserved
Flash block address. The size of the NAND Flash, as configured in OR n [PGS] and FMR[AL],
determines the number of bits of BLK that are issued to the EEPROM during block address phases.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
7
Figure 13-24. Flash Block Address Register
8
Table 13-27. FBAR Field Descriptions
16
17
13 14
All zeros
All zeros
All zeros
PI
Description
PI
21
Figure 13-25
MS
22
Figure
19
23
BLK
MS
20
13-24, locates the NAND Flash
21
and
Figure
Enhanced Local Bus Controller
CI
13-26, locates the
CI
Access: Read/Write
Access: Read/Write
Access: Read/Write
13-39
31
31
31

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