MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 59

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure
Number
9-33
9-34
9-35
9-36
9-37
9-38
9-39
9-40
9-41
9-42
9-43
9-44
9-45
9-46
9-47
9-48
9-49
9-50
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
10-15
10-16
10-17
10-18
10-19
10-20
10-21
10-22
10-23
Freescale Semiconductor
Shared Message Signaled Interrupt Index Register (MSIIR) ............................................... 9-38
Shared Message Signaled Interrupt Vector/Priority Register (MSIVPRs) ........................... 9-38
Shared Message Signaled Interrupt Destination Registers (MSIDRn) ................................. 9-39
Destination Register Summary ............................................................................................. 9-40
Vector/Priority Register Summary ........................................................................................ 9-41
External Interrupt Vector/Priority Registers (EIVPR0–EIVPR11) ....................................... 9-41
External Interrupt Destination Registers (EIDRs) ................................................................ 9-42
Internal Interrupt Vector/Priority Registers (IIVPRs) ........................................................... 9-43
Internal Interrupt Destination Registers (IIDRs) .................................................................. 9-44
Messaging Interrupt Vector/Priority Registers (MIVPRn) ................................................... 9-45
Messaging Interrupt Destination Registers (MIDRn) ........................................................... 9-46
Per-CPU Register Address Decoding in a Four-Core Device............................................... 9-48
Interprocessor Interrupt Dispatch Registers (IPIDR0–IPIDR3) ........................................... 9-48
Processor Core Current Task Priority Registers (CTPRn).................................................... 9-49
Processor Core Who Am I Registers (WHOAMIn) ............................................................. 9-50
Processor Core Interrupt Acknowledge Registers (IACKn)................................................. 9-51
End of Interrupt Registers (EOIn)......................................................................................... 9-51
PIC Interrupt Processing Flow Diagram for Each Core (n).................................................. 9-53
SEC Functional Modules ...................................................................................................... 10-3
Descriptor Format ............................................................................................................... 10-20
Header Dword ..................................................................................................................... 10-21
Pointer Dword ..................................................................................................................... 10-25
Link Table Entry ................................................................................................................. 10-26
Descriptors, Link Tables, and Parcels ................................................................................. 10-28
Fetch FIFO Enqueue Counter ............................................................................................. 10-36
Descriptor Finished Counter ............................................................................................... 10-36
Data Bytes In Counter......................................................................................................... 10-37
Data Bytes Out Counter ...................................................................................................... 10-37
Channel Configuration Register (CCR) .............................................................................. 10-38
Channel Status Register (CSR) ........................................................................................... 10-41
Current Descriptor Pointer Register.................................................................................... 10-43
Fetch FIFO Enqueue Register (FFER)................................................................................ 10-44
Gather/Scatter Link Table Entry Format and Memory Ranges .......................................... 10-46
EU Assignment Status Register (EUASR) ......................................................................... 10-50
ID Register .......................................................................................................................... 10-54
IP Block Revision Register ................................................................................................. 10-54
Master Control Register ...................................................................................................... 10-55
AESU Mode Register.......................................................................................................... 10-58
AESU Key Size Register .................................................................................................... 10-61
AESU Data Size Register ................................................................................................... 10-61
Interrupt Enable, Interrupt Status, and Interrupt Clear Registers....................................... 10-51
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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