MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 627

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When the UIIR is read, the associated DUART serial channel freezes all interrupts and indicates the
highest priority pending interrupt. While this read transaction is occurring, the associated DUART serial
channel records new interrupts, but does not change the contents of UIIR until the read access is complete.
Figure 12-7
Table 12-9
The bits contained in the UIIR registers are described in
Freescale Semiconductor
IID[3–0]
IID Bits
0b0001
0b0110
0b0100
0b1100
Bits
0–1
2–3
5–6
4
7
Offset UART0: 0x502, UART1: 0x602
Reset
IID2–1 Interrupt ID bits identify the highest priority interrupt that is pending as indicated in
Name
IID3
IID0
W
FE
Priority
—
Highest Receiver line status Overrun error, parity error, framing error, or
Second
Second
R
Level
describes the fields of the UIIR.
shows the bits in the UIIR.
—
FIFOs enabled. Reflects the setting of UFCR[FEN]
Reserved
Interrupt ID bits identify the highest priority interrupt that is pending as indicated in
along with IID2 only when a timeout interrupt is pending for FIFO mode.
IID0 indicates when an interrupt is pending.
0 The UART has an active interrupt ready to be serviced.
1 No interrupt is pending.
0
0
Received data
available
Character time-out
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Interrupt Type
FE
—
0
1
Figure 12-7. Interrupt ID Registers (UIIR)
Table 12-10. UIIR IID Bits Summary
Table 12-9. UIIR Field Descriptions
break interrupt
Receiver data available or trigger level
reached in FIFO mode
No characters have been removed from or
input to the receiver FIFO during the last 4
character times and there is at least one
character in the receiver FIFO during this time.
0
2
—
Interrupt Description
0
3
—
Description
Table
IID3
12-10.
0
4
IID2
0
5
Read the line status register.
Read the receiver buffer register or
interrupt is automatically reset if
the number of bytes in the receiver
FIFO drops below the trigger level.
Read the receiver buffer register.
How To Reset Interrupt
Table
Table
IID1
0
6
Access: Read only
12-10. IID3 is set
12-10.
—
IID0
1
7
DUART
12-9