MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 613

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.5
This section describes some programming guidelines recommended for the I
a recommended flowchart for I
The I
software must swap the bytes appropriately. This appropriate byte swapping is needed as I
byte registers. Also, an msync assembly instruction must be executed after each I
access to guarantee in-order execution.
The I
malfunctioning device may hold the bus captive. A good programming practice is for software to rely on
a watchdog timer to help recover from I
when the status bits returned after an interrupt are not consistent with what was expected due to illegal I
bus protocol behavior.
11.5.1
A hard reset initializes all the I
initializes the I
11.5.2
After initialization, the following sequence can be used to generate START:
Freescale Semiconductor
1. All I
2. Update I2CFDR[FDR] and select the required division ratio to obtain the SCL frequency from the
3. Update I2CADR to define the slave address for this device.
4. Modify I2CCR to select master/slave mode, transmit/receive mode, and interrupt-enable or
5. Set the I2CCR[MEN] to enable the I
1. If the device is connected to a multimaster I
2. Select master mode (set I2CCR[MSTA]) to transmit serial data and select transmit mode (set
2
2
C registers in this chapter are shown in big-endian format. If the system is in little-endian mode,
C controller does not guarantee its recovery from all illegal I
CCB (platform) clock. Note that the platform frequency must first be divided by two; see
Section 11.3.1.2, “I
disable.
whether the serial bus is free (I2CSR[MBB] = 0) before switching to master mode.
I2CCR[MTX]) for the address cycle.
Initialization/Application Information
Initialization Sequence
Generation of START
2
C registers must be located in a cache-inhibited page.
2
C unit:
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
2
C Frequency Divider Register
Figure 11-10. EEPROM Contents (continued)
1
2
2
C registers to their default states. The following initialization sequence
C interrupt service routines.
2
CRC[16–23]
CRC[24–31]
CRC[8–15]
CRC[0–7]
2
C bus hangs. The recovery routine should also handle the case
3
2
C interface.
4
2
5
C system, test the state of I2CSR[MBB] to check
6
(I2CFDR),” for more details.
7
Cyclic Redundancy
2
C bus activity. In addition, a
Check
2
C interface.
2
C register read/write
2
Figure 11-11
C registers are
I
2
C Interfaces
11-21
2
is
C